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AssigneeMassachusetts Institute of Technology
InventorsJack I. Raffel, John A. Yasaitis
Estimating the term…
An improved metal dual insulator semiconductor capacitor memory is disclosed. The memory contains a plurality of capacitor cells, each cell comprising a semiconductor substrate layer and a high conductivity layer sandwiching two insulator layers. The substrate is doped to provide avalanche breakdown in a surface depletion layer at a voltage comparable to the write voltage in the accumulation direction. The invention also provides a method of reading stored information without disturbing adjacent cells. A small variable voltage is applied across a "flat-band" portion of the hysteresis loop describing the voltage-capacitance relationship for the capacitor memory. A change or the absence of a change in the current through the capacitor indicates the state of the capacitor cell. Methods to fabricate the memory are also disclosed.
The process of writing in a capacitor memory array, the array comprising a plurality of isolated capacitor cells, each cell including at least a first conductive layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor layer, and a second conductive layer, the first conductive layers of said cells being grouped and interconnected into a plurality of word lines and the second conductive layers of said cells being grouped and interconnected into a plurality of bit lines, one each of said bit and word lines uniquely identifying a capacitor cell, and each cell having two capacitor states, the process including the steps of
The process of writing in a capacitor memory array, the memory comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, each capacitor cell exhibiting a capacitance versus applied potential hysteresis under the effect of an applied potential, including the steps of
The process of writing in a metal-nitride-oxide-silicon capacitor memory array, the memory comprising a plurality of isolated capacitor cells arranged in a rectilinear pattern, including the steps of
The process of writing in a capacitor memory array, the array comprising a plurality of isolated capacitor cells, each cell including at least a first conductive layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor layer, and a second conductive layer, the first conductive layers of said cells being grouped and interconnected into a plurality of word lines and the second conductive layers of said cells being grouped and interconnected into a plurality of bit lines, one each of said bit and word lines uniquely identifying a capacitor cell, and each cell having first and second capacitor states, the process including the steps of simultaneously
The process of writing in a capacitor memory array, the array comprising a plurality of isolated capacitor cells, each cell including at least a first conductive layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor layer, and a second conductive layer, the first conductive layers of said cells being grouped and interconnected into a plurality of word lines and the second conductive layers of said cells being grouped and interconnected into a plurality of bit lines, one each of said bit and word lines uniquely identifying a capacitor cell, and each cell having first and second capacitor states, the process including the steps of simultaneously
The process of reading a selected cell of a capacitor memory array, the array comprising a plurality of isolated capacitor cells, each cell including at least a first conductive layer, a first dielectric insulating layer, a second dielectric insulating layer, a doped semiconductor layer, and a second conductive layer, the first conductive layers of said cells being grouped and interconnected into a plurality of word lines and the second conductive layers of said cells being grouped and interconnected into a plurality of digit lines, one each of said digit and word lines uniquely identifying a capacitor cell, and each cell having two capacitance states, the process including the steps of
The process of reading a metal-nitride-oxide-silicon capacitor memory array having a plurality of digit lines and a plurality of word lines, and said memory including a plurality of cells, each cell having a plurality of charge states, including the steps of
Dependencies are inferred from the claim text.