US 4,234,957 A · Method and apparatus for generating timing phase error signals in PSK demodulators

Abstract

A circuit arrangement for combining a measure of the single phase error for a received data signal in a PSK demodulator with a measure of the direction of rotation of the receive data signal phasor between adjacent sample times for producing a timing phase error signal for controlling the phase of a local clock timing signal in the demodulator. In a demodulator producing a digital word defining differences between the phases of decoded phasors at adjacent sample times, a binary bit D.sub.k of the digital word may define the direction of rotation of the received signal phasor between the adjacent sample times. Sample values of the signal phase error signal in the demodulator are quantized into single binary bits E.sub.k indicating the sense of the signal phase error at sample times. In one circuit arrangement, binary bits E.sub.k and D.sub.k are combined in an exclusive-OR gate for producing a binary timing phase error bit M.sub.k. In a demodulator where phase differences are consecutively numbered clockwise in straight binary, the output of the exclusive-OR gate is inverted for producing binary timing phase error bits M.sub.k. In another circuit arrangement, binary bits A.sub.k and B.sub.k indicating the sense of the in-phase and quadrature-phase signal components for decoded phasors at a number of sample times are logically combined with signal phase error bits E.sub.k for producing binary timing phase error bits M.sub.k at sample times.

Claims52

Dependent claims

In a synchronous PSK data transmission system including receiver circuitry providing a local clock timing signal c(t) and receiving a data signal s(t) which includes data pulses coded during sample times into the phase of a carrier frequency signal, apparatus for producing a first error signal that is a timing phase error signal, comprising:

first means responsive to the receive data signal s(t) and the local clock timing signal c(t) for producing a second error signal e(t).sub.k that is a sample of the signal phase error signal e(t), the latter being a measure of the angular difference between the phase .theta.(t).sub.k of a received signal phasor obtained from the received data signal s(t) and the phase .theta..sub.k of a nearest allowable phasor member of an ideal set of signal phasors, where the .sub.k indicates the value thereof at a sample time;
the second error signal being an analog signal having a sense and magnitude;
second means responsive to the receive data signal s(t) and the local timing signal c(t) for producing a sample value d1.sub.k of a first directional signal d1 that is a measure of the direction of rotation of a received signal phasor between adjacent sample times, the first direction signal sample having a sense and magnitude that is a measure of the sine of the phase difference .DELTA..theta..sub.k between decisions as to the allowable phases .theta..sub.k of received signal phasors in adjacent symbol intervals;
and
third means combining the second error signal e(t).sub.k and the first directional signal sample d1.sub.k in a manner for producing a timing phase error signal g(t).sub.k that is a function of the product thereof and satisfies the expression sin (.DELTA..theta..sub.k) e(t).sub.k, and expansions thereof, the signal g(t).sub.k being a measure of the difference between the phase of the local timing signal and that of timing in the receive data signal for use in the receiver circuitry for adjusting the phase of the local timing signal there to be more nearly equal to the phase of timing in the received data signal.

2 more elements

In receiver circuitry of a synchronous PSK data transmission system receiving a data signal which includes data pulses coded during symbol intervals into the phase of a carrier frequency signal and producing a local clock timing signal, apparatus for producing in symbol intervals a binary timing phase error signal M.sub.k comprising:

first means responsive to the received data signal and the local clock signal for producing at sample times a binary signal E.sub.k representing the sense of the signal phase error, which is a measure of the angular difference between the phase .theta.(t).sub.k of a received signal phasor in the data signal and the associated phase .theta..sub.k of the nearest allowable member of an ideal set of signal phasors, where the subscript k indicates the value thereof at a sample time, and for producing binary signals A.sub.K and B.sub.K representing the sense of associated in-phase and quadrature phase component signals defining the nearest allowable phase .theta..sub.k that is associated with the phase .theta.(t).sub.k of a received signal phasor;
and
second means responsive to the binary signals A.sub.k , B.sub.k , and E.sub.k derived in a number of symbol intervals for producing binary timing phase error signals M.sub.k in symbol intervals indicating the sense of the error between the phase of the local clock signal and that of timing in the received data signal.

In a synchronous PSK data transmission system in which data pulses are coded during sample intervals into the phase of a carrier frequency signal, the improved method of producing a clock timing phase error signal for use in receiver circuitry for adjusting the phase of a local clock timing signal there to be more nearly equal to the phase of timing in a received data signal comprising the steps of:

producing a first error signal representative of the signal phase error signal at sample times;
producing at sample times a first directional signal representative of the direction of rotation of receive signal phasors in the received data signal between adjacent sample times;
and
combining the first error signal and the first directional signal for producing a timing phase error signal representative of the difference between the phase of the local timing signal and that of timing in the received signal.

1 more element

In a synchronous PSK data transmission system including receiver circuitry providing a local clock timing signal c(t) and receiving a data signal which includes data pulses coded during sample intervals into the phase of a carrier frequency signal, apparatus for producing a digital control word of one or more bits indicating the sense of the timing phase error, and thus the sense of the difference between the phase of the local timing signal and that of timing in the received data signal, for use in the receiver circuitry for adjusting the phase of the local timing signal there to be more nearly equal to the phase of timing in the received data signal, said apparatus comprising:

first means responsive to the received data signal and c(t) for producing a first digital word of at least one bit indicating the sense of the signal phase error, the first word designating which side of the nearest allowable phasor of an ideal set of signal phasors a received phasor obtained from the received data signal is on;
second means responsive to the received data signal and to the local timing signal for producing a second digital word of at least one bit indicating a direction of rotation of received signal phasors between adjacent clock sample times;
and
third means responsive to the first and second digital words for producing the digital control word indicating the sense of the timing phase error.

1 more element

Dependencies are inferred from the claim text.

Method and apparatus for generating timing phase error signals in PSK demodulators

Life of this patent

Method and apparatus for generating timing phase error signals in PSK demodulators

Life of this patent

Abstract

Claims52