Time-shared, multi-phase memory system with error checking and data correcting

In a data processing system, the combination comprising:

• a memory partitioned into a plurality of individually addressable memory portions, the accessing time of each memory portion requiring at least a plurality of operating cycles of said data processing system;
• addressing means coupled to said memory and responsive to an applied address for initiating accessing of selected locations in a plurality of different memory portions over a plurality of consecutively occurring operating cycles in a manner such that the accessing of only a particular selected one of said memory portions is initiated during an operating cycle;
• data accumulation means capable of simultaneously storing data read out from a plurality of said memory portions;
• and
• memory output means coupled to said memory and operative during a read operation for receiving data read out from each addressed selected location of a memory portion as it becomes available and operative during each of a plurality of said operating cycles for storing a predetermined portion of the received data from a selected one of said memory portions in a different designated location of said accumulation means until all of the predetermined portions of the received data read out from the addressed selected locations of said memory are simultaneously stored in said accumulation means;
• said memory output means including error checking and correcting means for detecting an error in the received data and for correcting at least one predetermined type of error prior to storage of the received data in said accumulation means.