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US 4,234,897 AGranted
DC Free encoding for data transmission
AssigneeAmpex Corporation
InventorJerry W. Miller
Life of this patent
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AssigneeAmpex Corporation
InventorJerry W. Miller
Estimating the term…
A method and apparatus provide for the elimination of any net DC component from the transmission of binary data sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states, e.g., 0's, are normally transmitted as signal transitions relatively early in respective bit cells, preferably at cell edge, and logical second bit states, e.g., 1's, are normally transmitted as signal transitions relatively late in respective bit cells, preferably at mid-cell, and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is suppressed. The onset of a sequence of second bit states following a first bit state that might introduce a DC component into the transmitted signal with normal transmission is detected by counting first bit states and producing a first indicating signal when the count is of parity indicating such sequence, and in response to the first indicating signal, a current bit and an adjacent bit the transmission of signal transitions is modified from the onset of such sequence to eliminate any DC component. Preferably, the possibly troublesome sequences are encoded by encoding pairs of second bit states by a single transition early in the first bit cell of the pair.
In a self-clocking transmission system for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in the respective bit cells and any transition relatively early in a bit cell following a transition relatively late in the next preceding bit cell is normally suppressed, apparatus for modifying the transmitted signal to remove any net DC component, said apparatus comprising first indicating means responsive to first bit states for counting the number of first bit states and producing at the onset of a sequence of second bit states following a first bit state a first indicating signal when the number of first bit states is of predetermined parity indicating any such sequence that might introduce a DC component into the transmitted signal with normal transmission, second indicating means responsive to bit states for producing a second indicating signal indicating whether the number of second bit states occurring in such sequence prior to a current bit is odd or even, and transition modifying means responsive to said first and second indicating signals and to the current bit and the next succeeding bit for modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component.
Apparatus in accordance with either one of claims 2 and 3 further including decoding means responsive to transmitted signal transitions for indicating the bit states of the binary data transmitted, said decoding means comprising synchronizing means responsive to transmitted signal transitions for providing timing signals identifying bit cell intervals, detection means responsive to said transmitted signal transitions and said timing signals by producing transition identifying signals identifying received signal transitions as relatively early or relatively late in respective bit cells, and bit state recognition means responsive to said transition identifying signals by indicating a bit cell as being in the second bit state under any of the conditions of
A self-clocking method for transmitting binary data bits sequentially in successive clocked bit cells of a transmission channel wherein logical first bit states are normally transmitted as signal transitions relatively early in the respective bit cells and logical second bit states are normally transmitted as signal transitions relatively late in the respective bit cells and any transition relatively late in the next preceding bit cell is normally suppressed, said method comprising detecting the onset of a sequence of second bit states following a first bit state that might introduce a DC component into the transmitted signal with normal transmission by counting the number of first bit states and producing a first indicating signal when the number of first bit states is of predetermined parity indicating such sequence, in response to bit states indicating whether the number of second bit states in such sequence prior to a current bit is odd or even by producing a second indicating signal indicative thereof, and in response to said first and second indicating signals and to the current bit and the next succeeding bit modifying the transmission of signal transitions from the onset of such sequence to eliminate any DC component.
Dependencies are inferred from the claim text.