PCM Recording and reproducing system
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorsKen Onishi, Kunimaro Tanaka
Life of this patent
Estimating the term…
Abstract
A reproduced PCM signal in the form of continuous frames is subjected to a code check after the separation of its frame synchronizing signals and then stored in a memory. If more than two consecutive frames are determined to include code errors resulting from a spliced portion of the associated PCM magnetic tape than those frames are prevented from being written into the memory but the latter is continuously read out by skipping the lost data and reading other data stored in the memory. Also the amount of data stored in the memory is sensed and maintained at a predetermined constant magnitude by controlling the speed of travel of the tape.
Claims7
An improvement in a PCM recording and reproducing system having a PCM converter means for converting an analog signal into a pulse code modulated signal, a PCM record medium having a plurality of record tracks disposed thereon, a recording means for recording the pulse code modulated signal on the plurality of record tracks of the PCM record medium in a predetermined pattern and a reproducing means for reproducing the pulse code modulated signal recorded on the PCM record medium, said improvement comprising:
- a memory means in said reproducing system having a predetermined storage capacity for storing data therein;
- a writing means connected to said memory means and having the reproduced pulse code modulated signal applied thereto, for continuously storing the reproduced pulse code modulated signal in said memory means;
- a reading means connected to said memory means for continuously reading the data stored in said memory means after a time delay from the time said data was stored in said memory means;
- a splice sensing means for sensing errors in the patterns in adjacent positions in a plurality of adjacent tracks in the direction transverse to the tracks and thereupon indicating the presence of a splice in the PCM record medium;
- and
- a writing suspension means connected to said writing means and said splice sensing means for suspending the writing of the pulse code modulated signal in said memory means upon generation of said splice signal.
An improvement in a PCM recording and reproducing system having a PCM converter means for converting an analog signal into a pulse code modulated signal, a PCM record medium having a plurality of record tracks disposed thereon, a recording means for recording the pulse code modulated signal on the plurality of record tracks of the PCM record medium in a predetermined pattern and a reproducing means for reproducing the pulse code modulated signal recorded on the PCM record medium, said improvement comprising:
- a memory means having a predetermined storage capacity for storing data therein;
- a writing means connected to said memory means and having the reproduced pulse code modulated signal applied thereto, for continuously storing the reproduced pulse code modulated signal in said memory means;
- a reading means connected to said memory means for continuously reading the data stored in said memory means a time delay after said data was stored in said memory means;
- a splice sensing means for generating a splice signal upon detection of a splice in the PCM record medium;
- a writing suspension means connected to said writing means and said splice sensing means for suspending the writing of the pulse code modulated signal in said memory means upon generation of said splice signal;
- and
- a writing speed control means connected to said memory means and said writing means for increasing the speed of storing the reproduced pulse code modulated signal in said memory means for a predetermined period of time when the amount of data stored in said memory means decreases below a predetermined amount.
An improvement in a PCM recording and reproducing system having a PCM converter means for converting an analog signal into a pulse code modulated signal, a PCM record medium having a plurality of record tracks disposed thereon, a recording means for recording the pulse code modulated signal on the plurality of record tracks of the PCM record medium in a predetermined pattern and a reproducing means for reproducing the pulse code modulated signal recorded on the PCM record medium, said improvement comprising:
- a memory means having a predetermined storage capacity for storing data therein;
- a writing means connected to said memory means and having the reproduced pulse code modulated signal applied thereto, for continuously storing the reproduced pulse code modulated signal in said memory means;
- a reading means connected to said memory means for continuously reading the data stored in said memory means a time delay after said data was stored in said memory means;
- a splice sensing means for generating a splice signal upon detection of a splice in the PCM record medium;
- a writing suspension means connected to said writing means and said splice sensing means for suspending the writing of the pulse code modulated signal in said memory means upon generation of said splice signal;
- a data amount sensor connected to said memory means and said splice sensor for generating a data amount signal indicative of the amount of data stored in said memory means upon generation of said splice signal;
- and
- a speed control means connected to said data amount sensor for controlling the speed of travel of the PCM record medium to set the amount of data stored in said memory means at a predetermined constant amount.
An improvement in a PCM recording and reproducing system having a PCM converter means for converting an analog signal into a pulse code modulated signal, a PCM record medium having a plurality of record tracks disposed thereon, a recording means for recording the pulse code modulated signal on the plurality of record tracks of the PCM record medium in a predetermined pattern and a reproducing means for reproducing the pulse code modulated signal recorded on the PCM record medium, said improvement comprising:
- a memory means having a predetermined storage capacity for storing data therein;
- a writing means connected to said memory means and having the reproduced pulse code modulated signal applied thereto, for continuously storing the reproduced pulse code modulated signal in said memory means;
- a reading means connected to said memory means for continuously reading the data stored in said memory means a time delay after said data was stored in said memory means;
- a splice sensing means for generating a splice signal upon detection of a splice in the PCM record medium;
- and
- a writing suspension means connected to said writing means and said splice sensing means for suspending the writing of the pulse code modulated signal in said memory means upon generation of said splice signal;
- said splice sensing means comprising:
- an error code check circuit having the reproduced pulse code modulated signal applied thereto for generating an error check signal for each frame of the reproduced pulse code modulated signal when a comparison of the data bits and the check bits of that frame indicates the probability of an error in the data bits of that frame is low;
- a first clock pulse generating means for generating a first series of clock pulses having the same repetition period as said error check signal;
- a plurality of flip-flop circuits, each having an input, an output and a clock terminal, said input of a first flip-flop having said error check signals applied thereto, said output of each flip-flop circuit connected to said input of a next succeeding flip-flop circuit, each of said clock terminals of said plurality of flip-flop circuit having said first series of clock pulses applied thereto, said plurality of flip-flop circuits for delaying said error check signals in an incremental manner;
- a second clock pulse generating means for generating a second series of clock pulses having the same repetition period as said first series of clock pulses and having a phase 180.degree. different from the phase of said first series of clock pulses;
- an AND gate having a plurality of inputs, said flip-flop circuit outputs and said second series of clock pulses applied to respective inputs;
- and
- a R-S flip-flop circuit having a reset input connected to said AND gate and a set input connected to said NOR gate for generating said splice signal when set and not generating said splice signal when reset.
An improvement in a PCM recording and reproducing system having a PCM converter means for converting an analog signal into a pulse code modulated signal, a PCM record medium having a plurality of record tracks disposed thereon, a recording means for recording the pulse code modulated signal on the plurality of record tracks of the PCM record medium in a predetermined pattern and a reproducing means for reproducing the pulse code modulated signal recorded on the PCM record medium, said improvement comprising:
- a memory means having a predetermined storage capacity for storing data therein;
- a writing means connected to said memory means and having the reproduced pulse code modulated signal applied thereto, for continuously storing the reproduced pulse code modulated signal in said memory means;
- a reading means connected to said memory means for continuously reading the data stored in said memory means a time delay after said data was stored in said memory means;
- a splice sensing means for generating a splice signal upon detection of a splice in the PCM record medium;
- a writing suspension means connected to said writing means and said splice sensing means for suspending the writing of the pulse code modulated signal in said memory means upon generation of said splice signal;
- and
- a control circuit means connected to said writing means having a writing counter circuit for determining the addresses for storage of the reproduced pulse code modulated signal in said memory means, and a gate means connected to said writing counter circuit and said splice sensing means for preventing change of said address determined by said writing counter circuit upon generation of said splice signal.
Dependencies are inferred from the claim text.