Programmable frequency divider and method

A frequency divider for dividing the frequency of an applied binary signal by a programmable integer divisor comprising:

• first bistable switching element having a first input connected to receive an applied binary signal with the frequency to be divided, having a second input, and having an output which generates a frequency divided signal equivalent to the state of the second input at the occurrence of the most recent signal at the first input;
• second bistable switching element having a first input connected to receive an applied binary signal with the frequency to be divided, having a second input connected to receive the output of the first bistable element and having an output which generates a signal equivalent to the logical inverse of the state of the second input at the occurrence of the most recent signal at the first input;
• selector means having a first input connected to receive the output of the first bistable switching element, having a second input connected to receive an applied divisor select signal for selecting a partial divisor of three or four, and having an output which generates a signal equivalent to the logical inverse of the logical OR combination of the inputs;
• and
• means coupling the output of the second bistable switching element and the output of the selector means to the second input of said first bistable switching element.

Apparatus for dividing the frequency of an applied signal by a programmable integer divisor comprising:

• divider means having a control input and having another input to receive applied signal for dividing the frequency thereof by an integer determined by a signal appearing on the control input;
• shift register means including a plurality of intercoupled data cells having outputs and having inputs for receiving applied data signals, the shift register means having a data loading control input for enabling the data cells to accept and store data signals which are applied to inputs of the data cells for parallel loading therein in response to a signal applied to the data loading control input thereof, said shift register means including a data shift input for sequentially shifting stored data signal between data cells in response to a signal applied to the data shift input thereof;
• means coupled to the data shift input for applying the divided frequency from the divider means thereto;
• means coupled to the shift register means for applying to the data loading control input thereof a signal from an output of a data cell representative of a data signal stored therein;
• means coupled to the control input of the divider means for applying thereto a signal from a selected output of a data cell representative of a data signal stored therein;
• and
• means coupled to an output of data cell for producing the divided frequency output.

Method of dividing the frequency of an applied signal comprising the steps of:

• selecting a plurality of partial divisors, wherein the sum of integer multiples of the partial divisors equals the desired divisor;
• producing a signal having a plurality of logic states which may be logically shifted relative to a reference condition of logic states, which signal exhibits a change in the logic state relative to the reference condition only after an integer number of logical shifts of the signal where said integer number is equal to the sum of said integers which are multipliers of the partial divisors, and which plurality of logic states may be decoded to select each of said plurality of partial divisors a number of times equal to the integer multiplier of said selected partial divisors;
• decoding the signal of logic states to select one of said plurality of partial divisors;
• dividing an applied signal by the selected partial divisor to generate a partially divided output of the applied signal;
• logically shifting the signal of logic states in logic increments in a constant direction relative to the reference condition for each period of said partially divided output;
• repeating the decoding, dividing and logical shifting steps;
• generating an output signal having the desired divided frequency of the applied signal from the occurrence of said change in the logic state with respect to the reference condition;
• and
• restoring the signal of logic states to its original condition relative to the reference condition on the occurrence of the output signal generated by said change in the logic state with respect to the reference condition.