US 4,233,682 AGranted

Fault detection and isolation system

AssigneeSperry Corporation

InventorsHarris L. Liebergot, Richard M. Sedmak

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Abstract

The invention provides data processing duplication and internal error checking within an integrated circuit chip at intermediate points along the logic chain. In one aspect of the invention, duplicate functional logic within the chip is utilized together with multiple fault detectors to provide error checking of the primary logic chain, mechanical interconnection failures, and power and clock pulse checking. The detectable failures are both transient and hard failures. Other problems are in addition resolvable by utilization of duplicate complementary logic in place of duplicate functional logic, such other problems including chip contamination during manufacture, mask problems and functional design problems. The multiple fault detectors provide a multiplicity of error signals which are multiplexed within the chip to produce encoded output error signals each of which designates the fault which has been detected within the chip. These encoded error signals are routed to a special error handling chip which receives encoded error signals from a large number of places, such as a group of chips or circuit cards, and by correlating the information contained in the encoded error signals is able to identify the source of the error as a particular VLSI chip, the interconnections between VLSI chips, a particular circuit card, a power supply line to a circuit card or a group of such cards, or other faults.

Claims14

Dependent claims

An integrated circuit chip comprising in combination,

(a) a first data processing chain having an input circuit and a first plurality of output circuits spaced at different points along said first data processing chain, at least one of said first plurality of output circuits being an intermediate output circuit,
(b) a second data processing chain having an input circuit and a second plurality of output circuits spaced at different points along said second data processing chain, at least one of said second plurality of output circuits being an intermediate output circuit,
(c) input signal connections for coupling external signals to said chip,
(d) means connecting at least some of said input signal connections to said input circuits of both of said first and second data processing chains,
(e) at least one comparator circuit having a first input circuit permanently coupled to said at least one intermediate output circuit of said first processing chain for receiving signals therefrom, a second input circuit permanently coupled to said at least one intermediate output circuit of said second processing chain for receiving signals therefrom, and an output circuit,
said at least one intermediate output circuit points of said data processing chains being the equivalent to each other along the processing path in each chain, and said comparator producing at its output circuit a first signal indicating the occurrence of an error when the input signals to the said comparator represent different data and producing at its output circuit a second signal when the input signals to the said comparator represent the same data.

3 more elements

An integrated circuit chip comprising in combination,

(a) a first data processing chain having an input circuit and a first plurality of output circuits spaced at different points along said first data processing chain, at least one of said first plurality of output circuits being an intermediate output circuit,
(b) a second data processing chain having an input circuit and a second plurality of output circuits spaced at different points along said second data processing chain, at least one of said second plurality of output circuits being an intermediate output circuit,
(c) input signal connections for coupling external signals to said chip,
(d) means connecting at least some of said input signal connections to said input circuits of both of said first and second data processing chains,
(e) at least one comparator circuit having a first input circuit coupled to said at least one intermediate output circuit of said first processing chain for receiving signals therefrom, a second input circuit coupled to said at least one intermediate output circuit of said second processing chain for receiving signals therefrom, and an output circuit, said at least one intermediate output circuit points of said data processing chains being the equivalent to each other along the processing path in each chain, and said comparator producing at its output circuit a first signal indicating the occurrence of an error when the input signals to the said comparator represent different data and producing at its output circuit a second signal when the input signals to the said comparator represent the same data,
(f) at least another comparator circuit having, a first input circuit coupled to another of said first plurality of output circuits of said first processing chain for receiving signals therefrom, a second input circuit coupled to another of said second plurality of output circuits of said second chain for receiving signals therefrom, and an output circuit, said at least another comparator circuit producing at its output circuit a first signal indicating the occurrence of an error when the input signals to the said another comparator represent different data and producing at its output circuit a second signal when the input signals to the said another comparator represent the same data,
(g) an error encoding circuit having a plurality of input circuits and an output circuit, the output circuits of said at least one comparator circuit and said at least another comparator circuit being coupled to separate ones of said plurality of input circuits of said error encoding circuit, and said error encoding circuit being effective responsive to receipt of said first and second signals from said comparator circuits to generate at its output circuit encoded signals designating the sources of processing errors in said integrated circuit chip.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 05/915,838Filed 15 Jun 1978
Granted: 11 Nov 1980
Term ends: Not estimatedThe source records don’t support an estimate.

Classification4 codes

G06F 11/1608
Error detection or correction of the data by redundancy in hardware: error detection by comparing the output signals of redundant hardware
G06F 11/0751
Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of…
G06F 11/079
Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of…
G06F
Computing and data processing