US 4,233,673 A · Electrically resettable non-volatile memory for a fuse system

Abstract

A non-volatile memory has a plurality of storage bits, each bit comprising an insulated gate field effect transistor having a variable threshold voltage and selectively set to first and second stable threshold voltages in response to the application of positive and negative polarizing voltages between the gate and source thereof. The threshold voltage state of the transistor is determined by applying a read voltage having a magnitude greater than the first stable threshold voltage and less than the second stable threshold voltage, the transistor being activated only if it has assumed the first threshold voltage. Complementary addressing circuitry selectively and sequentially couples the data bits of a serial data word, received at a data terminal, to corresponding memory bits for storage in the memory. The memory bits are initially cleared by applying a positive polarizing voltage to the transistors to set them to the first stable threshold state. The addressing circuitry selectively applies a negative polarizing voltage to the transistors to set them to the second stable threshold state in accordance with the data word. The addressing circuitry also provides for interrogation of the memory by applying a read voltage to the bits in sequence and coupling the bits to the data terminal. A fire command generated by the firing of a projectile, such as an artillery shell, transfers the information in the memory to a counter. The counter is then operated at a predetermined clock rate until overflow occurs for generating a signal for detonating the explosive projectile.

Claims10

Dependent claims

An electrically resettable memory for storing a plural bit data word comprising:

a plurality of memory storage bits, each of said storage bits comprising a variable threshold voltage transistor having a first and a second stable state,
means for applying a negative polarizing voltage to the gate of each of said storage transistors,
memory clearing means for applying a positive polarizing voltage to said storage bits to set said storage bits to a first stable threshold voltage state,
means for supplying a bi-level data signal representing a plural bit data word,
addressing means for sequentially addressing said plurality of storage bits and for coupling the bi-level data signal to the source of said addressed storage bit transistors to enable storage of one of the bi-levels of the data signal such that a negative polarizing voltage is established between the gate and source thereby setting said addressed transistor to said second stable state, and to enable storage of the other of the bi-levels of the data signal such that a voltage substantially less than the polarizing voltage is established between the gate and source thereby retaining the first stable state of said addressed transistor set by said memory clearing means, and
write means for selectively applying a negative polarizing voltage to an addressed storage bit to set said addressed storage bit to the second stable threshold voltage state in accordance with a predetermined, corresponding data bit.

3 more elements

An electrically resettable memory for a fuse system for storing a plural bit data word defining a predetermined time interval between a first random event and a second event, comprising:

a plurality of memory storage bits, each of said storage bits comprising a variable threshold voltage transistor,
memory clearing means for applying a positive polarizing voltage to the body, and a ground potential voltage to the gate of each of said storage bits in common to set said storage bits to a first stable threshold voltage state corresponding to a cleared condition of said memory,
means for sequentially addressing said plurality of storage bits by selective connection to the sources of said storage bit transistors,
write means for applying a negative polarizing voltage to the gate of each of said storage bit transistors in common and for supplying a bi-level, serial data signal representing the plural bit data word to the addressing means for selective coupling thereby to the sources of the sequentially addressed storage bits to establish, for one of the bi-levels of the data signal, a negative polarizing voltage between the gate and source of an addressed bit for setting to said second stable state, and to establish, for the other of the bi-levels of the data signal, a voltage substantially less than the polarizing voltage between the gate and source of an addressed bit for retaining the first stable state of the transistor set by said memory clearing means,
a main counter having a plurality of stages coupled to respectively associated storage bits of said memory,
means responsive to a first command defining the first read out event for transferring the plural bit data word stored in said memory bits to the corresponding stages of the counter for initializing the counter and to effect stepping of the counter until overflow occurs, and
means responsive to overflow of the counter for generating a detonate command defining the second event.

4 more elements

Dependencies are inferred from the claim text.

Electrically resettable non-volatile memory for a fuse system

Life of this patent

Electrically resettable non-volatile memory for a fuse system

Life of this patent

Abstract

Claims10