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AssigneesNippon Telegraph & Telephone Public Corporation, Hitachi, Ltd.
InventorsNakahiko Yamaguchi, Susumu Hibi, Shigeru Yoshizawa, Shoji Yoshimoto, Akira Kobayashi
Estimating the term…
Method and apparatus for testing a magnetic bubble memory are disclosed wherein a most severe magnetic bubble domain arrangement which fully causes the ununiformity of magnetic interaction between magnetic bubble domains is experimentally determined, and a basic pattern [P] and a test information pattern determining an arrangement of the basic patterns [P] and complementary patterns [P] thereof for realizing that magnetic bubble domain arrangement are stored in memory units, respectively, and the basic patterns [P] and the complementary patterns [P] are sequentially read out in accordance with the test information pattern to generate magnetic bubble domain trains in a storage area of the magnetic bubble memory. The magnetic bubble domain trains are then read out by a magnetic bubble detector and the read-out signals are converted to logical signals by a sense amplifier unit and the logical signals are synchronized with logical signals corresponding to the test information pattern and compared therewith to produce an identity or non-identity signal and thus the disclosed method and apparatus for testing the magnetic bubble memory can exactly evaluate a memory characteristic of the magnetic bubble memory.
A method for testing a magnetic bubble memory comprising the steps of:
A test apparatus for a magnetic bubble memory including a plurality of rectangularly arranged planes each comprising m minor loops each consisting of 2.times.n bits comprising a magnetic thin film for generating and maintaining magnetic bubble domains and soft magnetic material thin films arranged on said magnetic thin film, using a test information pattern stored in a storage area of said magnetic bubble memory, said test information pattern determining an arrangement of basic patterns [P] and complementary patterns [P] thereof, said basic pattern including "0" information at at least one bit position in a first n-bit minor loop in said storage area and "1" information at remaining bit positions, and including "0" information at a stationary bit position in a second minor loop which is adjacent to said first minor loop, said stationary bit position in said second minor loop being displaced by l-bit positions from the "0" information bit position in said first minor loop, and including "0" information at bit positions in third to m-th minor loops each of which bit positions is displaced by l-bit positions from the bit position in the preceding minor loops, said complementary pattern [P] being a complementary pattern to said basic pattern [P], that is, "1" information bits and "0" information bits in said basic pattern [P] having been replaced with "0" information bits and "1" information bits, respectively, in said complementary pattern [P];
Dependencies are inferred from the claim text.