US 4,233,618 AGranted

Integrated circuit with power transistor

AssigneeSprague Electric Company

InventorRobert C. Genesi

Life of this patent

Estimating the term…

Loading patent…

Abstract

An integrated silicon circuit includes a plurality of high current power transistors. Each of the power transistors is formed in an epitaxial pocket of N-type conductivity being defined by a surrounding P-type isolation wall. A large N-type plug region occupies a central position in the pocket over which lies a large aluminum collector terminal pad. The P-type base region is an elongated strip region essentially surrounding the N-type plug. An elongated emitter lies within the base strip region and is contacted along its entire length by a metal layer that extends broadly in radial directions from the pocket to contact the isolation wall and leading to a ground terminal pad of the entire integrated circuit. The ratio of the current carrying capability of this power transistor to the silicon area occupied by the transistor is high.

An integrated semiconductor circuit having a high-current power transistor comprising:

(a) a semiconductor substrate of one conductivity type;
(b) an epitaxial layer of the opposite conductivity type on said substrate;
(c) a closed annular isolation-wall region of said one type being formed in said epitaxial layer, said wall region extending through said epitaxial layer from the outer surface thereof to the interface between said epitaxial layer and said substrate, defining within said epitaxial layer a pocket-region;
(d) an annular strip region of said one type being formed in said pocket region, extending from said surface only part way through said epitaxial layer, and being spaced inwardly from said wall region to serve as the base region of said transistor;
(e) an elongated region of said opposite type being formed within and along said strip region and extending to said surface to serve as the emitter of said transistor;
(f) a collector contact plug region of said opposite conductivity type being formed in a central portion of said pocket, being spaced inwardly from said annular strip region, extending from said surface through said epitaxial layer, and having at the periphery thereof a substantially greater electrical conductivity than that of the immediately adjacent portion of said pocket region;
(g) a metal collector-termination pad overlying and contacting said plug region at said surface, the periphery of said metal pad being substantially coincident with said periphery of said underlying plug region, said collector-termination pad having an area no smaller than 10.sup.4 square microns;
(h) one metal layer contacting at said surface said elongated emitter region substantially along the entire length thereof;
and
(i) another metal layer contacting at said surface said base strip region essentially along the entire length thereof, said another layer lying between and being spaced from said collector termination pad and said one metal layer.

7 more elements

Facts

Application

05/929,759Filed 31 Jul 1978

Granted

11 Nov 1980

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

H10D 62/133
Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions: emitter…
H10D 64/231
Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes: emitter or collector…
H10W 10/031
Manufacture or treatment: of isolation regions comprising PN junctions
H10W 10/30
Isolation regions in semiconductor bodies between components of integrated devices: isolation regions comprising PN junctions

Abstract

Claims12