Multi-matrix display system having matrix display panel with uncrossed connections on substrates

A matrix display system comprising:

• a display panel including picture elements arranged in matrix having a plurality of rows and columns, a plurality of row electrodes commonly connected to at least two columns of said picture elements, a plurality of column electrodes arranged transversely to each of said row electrodes, and a display material electrically excitable and arranged between said row electrodes and at least one of said column electrodes for constituting a plurality of picture elements to be displayed when said row and column electrodes are selectively energized, and
• a drive circuit for selectively applying signals between said row electrodes and said column electrodes, said display panel having n rows of picture elements arranged to face the respective rows of said row electrodes, 2n rows of said picture elements facing any two adjacent rows of said row electrodes being reversed from one row electrode to the next row electrode by n column electrodes, where n is an integer of at least 2, and the first column electrode connecting the picture element of the first row facing the first row electrode with the picture element of the n-th row facing the second row electrode, the second column electrode connecting the picture element of the second row facing the first row electrode with the picture element of the (n-1)th row facing the second row electrode, and the n-th column electrode connecting the picture element of the n-th row facing the first row electrode with the picture element of the first row facing the second row electrode, and
• said drive circuit having n line memories, and n column electrodes per column of said picture elements being connected to different line memories, and each line memory memorizing picture data signals equal to the column number of the picture elements and simultaneously outputting all data in order to drive each column electrode, the order of memorizing said picture data signals in n line memories corresponding to the order of the line memory connected to first, second, . . . the nth column electrodes against said row electrode, and the following row electrode being connected in sequence to the n-th, (n-1)th, . . . second, first column electrodes.