Electronic circuit for use in a digital circuit which prevents passage of pulses having a pulse width narrower than a predetermined value
AssigneeFujitsu Limited
InventorsYukio Takahashi, Kazuhiro Toyoda
Life of this patent
Estimating the term…
Abstract
An electronic circuit is used in a digital circuit to prevent the passage of pulses having a pulse width narrower than a predetermined value. According to the present invention, the electronic circuit is composed of a first circuit, having a delay circuit and a first gate with two input terminals, for generating an output when a pulse width of an input pulse is larger than a delay time of the delay circuit, and a second circuit for input pulses of width greater than the delay time which forms an output pulse having a pulse width which is the same as that of the input pulse of the first circuit.
Claims21
An electronic circuit for use in a digital circuit to prevent the passage of pulses having pulse width narrower than a predetermined value and for preserving the pulse width of transmitted pulses, said electronic circuit comprising:
- a first circuit for receiving an input pulse, said first circuit comprising a delay circuit and a first gate having two input terminals, one of said two input terminals of said first gate comprising means for receiving said input pulse to said first circuit and the other of said two input terminals comprising means for receiving a delayed pulse corresponding to said input pulse as a result of passing through said delay circuit, said gate of said first circuit further comprising means for generating an output pulse of said first circuit when said input pulse has a pulse width larger than a predetermined delay time corresponding to said delay circuit;
- a second circuit comprising means for receiving the output pulse of said first circuit and for forming a pulse having a pulse width which is substantially the same as that of said input pulse of said first circuit when said input pulse has a pulse width larger than that corresponding to said predetermined delay time, said means of said second circuit comprising:
- a second gate, and a group of first delay gates connected in series, the total delay time of said group of first delay gates being substantially the same as said predetermined width value, and the output of said first circuit and of each said first delay gates being input to said second gate.
An electronic circuit for use in a semi-conductor memory device comprising:
- a first input terminal for receiving a circuit input pulse,
- a first delay circuit comprising an input terminal connected to said first input terminal and an output terminal, said first delay circuit having a corresponding first delay time,
- a first gate comprising two input terminals and an output terminal, one of said two input terminals being connected to said first input terminal and the other being connected to said output terminal of said first delay circuit, said first gate and said first delay circuit comprising further means for generating a first output pulse on said output terminal of said first gate when an input pulse is supplied to said first input terminal with a pulse width larger than a predetermined delay time corresponding to said first delay circuit,
- a second delay circuit comprising an input terminal connected to said output terminal of said first gate and having at least two output terminals,
- a second gate comprising a plurality of input terminals, one of said input terminals of said second gate being connected to said output terminal of said first gate and at least two other of said plurality of input terminals of said second gate being connected to said at least two output terminals of said second delay circuit, said second delay circuit and said second gate further comprising means for providing a second output pulse having a pulse width which is substantially the same as that of said circuit input pulse when said circuit input pulse has a pulse width greater than said predetermined delay time, and
- said second delay circuit comprising a group of second delay gates connected in series, the total delay time of said group of second delay gates being the same as that of said predetermined width value, each of said second delay gates having an output terminal connected to one of said input terminals of said second gate.
Dependencies are inferred from the claim text.