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US 4,233,500 AGranted
Method and apparatus for providing a digital output in response to an analog input and for providing an analog output in response to a digital input
AssigneePhillips Petroleum Company
InventorLeroy D. Cordill
Life of this patent
Estimating the term…
Abstract
The accuracy of the conversion of an analog signal to digital form is improved by amplifying the input signal by different factors and automatically utilizing the highest amplified input signal which has a voltage level within operational limitations in the analog to digital conversion process. Output data from a digital computer, based on the input data, is converted from digital form to analog form and is routed to a required location by the use of control logic and optically isolated digital signals used to address other computers.
Claims47
Apparatus comprising:
- means for producing a first analog signal;
- means for producing an offset voltage signal;
- means for combining said first analog signal and said offset voltage signal to produce a second analog signal;
- first amplifier means;
- means for providing said second analog signal as an input to said first amplifier means to thereby establish an amplified second analog signal having a first predetermined relationship to said second analog signal;
- an analog-to-digital converter means;
- means for establishing a third analog signal representative of the highest voltage level desirable as an input signal into said analog-to-digital converter means;
- means for comparing said amplified second analog signal to said third analog signal and for providing said amplified second analog signal as an input signal to said analog-to-digital converter means to be converted into a first digital signal if the voltage level of said amplified second analog signal does not exceed the voltage level of said third analog signal;
- means for providing said second analog signal as an input signal to said analog-to-digital converter means to be converted into a first digital signal if the voltage level of said amplified second analog signal exceeds the voltage level of said third analog signal, said offset voltage signal having a voltage level which will reduce the voltage level of said first analog signal to enable said amplified second analog signal to be provided as an input to said analog-to-digital converter means if the difference between the voltage level of said first analog signal, multiplied by the amplification factor of said first amplifier means, and the voltage level of said third analog signal does not exceed the maximum available absolute voltage level of said offset voltage signal multiplied by the amplification factor of said first amplifier means.
6 more elements
Apparatus comprising:
- a digital computer means for producing a first digital signal and for producing control signals to route said first digital signal to a desired destination;
- a plurality of digital-to-analog converter means, for receiving and converting a digital signal to an analog signal and for supplying said analog signal to a desired destination, each of said plurality of said digital-to-analog converter means having an input terminal and an output terminal;
- a plurality of first data register means, for receiving said first digital signal from said first digital computer means and supplying said first digital signal to at least a respective one of said plurality of said digital-to-analog converter means, each of said plurality of said first data register means having first and second input terminals and an output terminal;
- means for connecting the input terminal of each one of said plurality of said digital-to-analog converter means to the output terminal of a respective one of said plurality of said first data register means;
- a first OR gate means having first and second input terminals and an output terminal;
- a first inverter means having an input terminal and an output terminal;
- means for connecting said first digital computer means to the first input terminal of said first OR gate means and for supplying a second digital signal, which is equal to logic 0 when said first digital signal is available to be written out to said plurality of said first data register means, from said first digital computer means to the first input of said first OR gate means;
- means for connecting said first digital computer means to the input terminal of said first inverter means and for supplying an address enable digital signal, which is equal to logic 1 when it is desired to enable the digital-to-analog conversion process for said first digital data signal, from said first digital computer means to the input of said first inverter means;
- means for connecting the output terminal of said first inverter means to the second input terminal of said first OR gate means;
- a four bit to ten bit decoder means having first, second, third, and fourth input terminals and first through tenth output terminals;
- means for supplying a four bit digital address signal from said first digital computer means to said first, second, third, and fourth input terminals of said four to ten bit decoder means;
- a first AND gate means having first and second input terminals and an output terminal;
- a second AND gate means having first and second input terminals and an output terminal;
- a third AND gate means having first and second input terminals and an output terminal;
- means for connecting the first and third output terminals of said four bit to ten bit decoder means to the first and second inputs respectively of said first AND gate means;
- means for connecting the fifth and seventh output terminals of said four bit to ten bit decoder means to the first and second inputs respectively of said second AND gate means;
- means for connecting the output terminal of said first AND gate means to the first input terminal of said third AND gate means and for connecting the output terminal of said second AND gate means to the second input terminal of said third AND gate means;
- second OR gate means having first and second input terminals and an output terminal;
- means for connecting the output terminal of said first OR gate means to the first input terminal of said second OR gate means and for connecting the output terminal of said third AND gate means to the second input terminal of said second OR gate means;
- third OR gate means having first and second input terminals and an output terminal;
- means for establishing a clock signal;
- second inverter means having an input terminal and an output terminal;
- means for supplying said clock signal to the input terminal of said second inverter means;
- means for connecting the output terminal of said second inverter means to the first input terminal of said third OR gate means and for connecting the output terminal of said second OR gate means to the second input terminal of said third OR gate means;
- a second data register means having first and second input terminals and an output terminal;
- means for supplying the most significant bits of said first digital signal to the first input of said second data register means;
- means for connecting the output terminal of said third OR gate means to the second input of said second data register means to provide a second enabling signal to said second data register means;
- means for storing the most significant bits of said first digital signal in said second data register means until the least significant bits of said first digital signal have also been transmitted from said first digital computer means and then transmitting the combination of the most significant bits and the least significant bits of said first digital signal to the first input terminal of said plurality of said first data register means;
- and
- means for automatically selecting one of said plurality of said first data register means to be enabled and for providing a first enabling signal having a predetermined logic value from said first digital computer means to the second input of the selected one of said plurality of said first data register means to enable the selected one of said plurality of said first data register means and initiate the digital-to-analog conversion of said first digital signal.
27 more elements
Apparatus comprising:
- a digital computer means for producing a first digital signal and for producing control signals to route said first digital signal to a desired destination;
- a plurality of digital-to-analog converter means, for receiving and converting a digital signal to an analog signal and for supplying said analog signal to a desired destination, each of said plurality of said digital-to-analog converter means having an input terminal and an output terminal;
- a plurality of first data register means, for receiving said first digital signal from said first digital computer means and supplying said first digital signal to at least a respective one of said plurality of said digital-to-analog coverter means, each of said plurality of said first data register means having first and second input terminals and an output terminal;
- means for connecting the input terminal of each one of said plurality of said digital-to-analog coverter means to the output terminal of a respective one of said plurality of said first data register means;
- a first OR gate means having first and second input terminals and an output terminal;
- a first inverter means having an input terminal and an output terminal;
- means for connecting said first digital computer means to the first input terminal of said first OR gate means and for supplying a second digital signal, which is equal to logic 0 when said first digital data signal is available to be written out to said plurality of said first data register means, from said first digital computer means to the first input of said first OR gate means;
- means for connecting said first digital computer means to the input terminal of said first inverter means and for supplying an address enable digital signal, which is equal to logic 1 when it is desired to enable the digital to analog conversion process for said first digital data signal, from said first digital computer means to the input of said first inverter means;
- means for connecting the output terminal of said first inverter means to the second input terminal of said first OR gate means;
- a first four bit to ten bit decoder means having first, second, third, and fourth input terminals and first through tenth output terminals;
- means for supplying a first four bit digital address signal from said first digital computer means to the first, second, third, and fourth input terminals of said first four to ten bit decoder means;
- a second OR gate means having first and second input terminals and an output terminal;
- means for connecting the output terminal of said first OR gate means to the first input terminal of said second OR gate means;
- means for connecting a selected one of the output terminals of said first four bit to ten bit decoder means to the second input terminal of said second OR gate means;
- means for selecting one of a plurality of said cards, each having a plurality of said first data register means, by driving the output terminal of said second OR gate low in response to said first four bit digital address;
- a second four bit to ten bit decoder means having first, second, third, and fourth input terminals and first through tenth output terminals;
- means for supplying a second four bit digital address signal from said first digital computer means to the first, second, third, and fourth input terminals of said second to ten bit decoder means;
- a first AND gate means having first and second input terminals and an output terminal;
- a second AND gate means having first and second input terminals and an output terminal;
- a third AND gate means having first and second input terminals and an output terminal;
- means for connecting the first and third output terminal of said second four bit to ten bit decoder means to the first and second inputs respectively of said first AND gate means;
- means for connecting the fifth and seventh output terminals of said second four bit to ten bit decoder means to the first and second inputs respectively of said second AND gate means;
- means for connecting the output terminal of said first AND gate means to the first input terminal of said third AND gate means and for connecting the output terminal of said second AND gate means to the second input terminal of said third AND gate means;
- a third OR gate means having first and second input terminals and an output terminal;
- means for connecting the output terminal of said second OR gate means to the first input terminal of said third OR gate means and for connecting the output terminal of said third AND gate means to the second input terminal of said third OR gate means;
- fourth OR gate means having first and second input terminals and an output terminal;
- means for establishing a clock signal;
- second inverter means having an input terminal and an output terminal;
- means for supplying said clock signal to the input terminal of said second inverter means;
- means for connecting the output terminal of said second inverter means to the first input terminal of said fourth OR gate means and for connecting the output terminal of said third OR gate means to the second input terminal of said fourth OR gate means;
- a second data register means having first and second input terminals and an output terminal;
- means for supplying the most significant bits of said first digital signal to the first input of said second data register means;
- means for connecting the output terminal of said fourth OR gate to the second input of said second data register means to provide a second enabling signal to said second data register means;
- means for storing the most significant bits of said first digital signal in said second data register means until the least significant bits of said first digital signal have also been transmitted from said first digital computer means and then transmitting the combination of the most significant bits and the least significant bits of said first digital signal for transmission to the first input terminal of said plurality of said first data register means on the card selected;
- and
- means for automatically selecting one of said plurality of said first data register means to be enabled and for providing a first enabling signal having a predetermined logic value from said first digital computer means to the second input of the selected one of said plurality of said first data register means to enable the selected one of said plurality of said first data register means and initiate the digital-to-analog conversion of said first digital signal.
33 more elements
Apparatus comprising:
- a digital computer means for producing a first digital signal and for producing control signals to route said first digital signal to a desired destination;
- a plurality of digital-to-analog converter means, for receiving and converting a digital signal to an analog signal and for supplying said analog signal to a desired destination, each of said plurality of said digital-to-analog converter means having an input terminal and an output terminal;
- a plurality of first data register means, for receiving said first digital signal from said first digital computer means and supplying said first digital signal to at least a respective one of said plurality of said digital-to-analog converter means, each of said plurality of said first data register means having first and second input terminals and an output terminal;
- means for connecting the input terminal of each one of said plurality of said digital-to-analog converter means to the output terminal of a respective one of said plurality of said first data register means;
- means for providing said first digital signal to the first input of said plurality of said first data register means;
- a first OR gate means having first and second input terminals and an output terminal;
- a first inverter means having an input terminal and an output terminal;
- means for connecting said first digital computer means to the first input terminal of said first OR gate means and for supplying a second digital signal, which is equal to logic 0 when said first digital data signal is available to be written out to said plurality of said first data register means, from said first digital computer means to the first input of said first OR gate means;
- means for connecting said first digital computer means to the input terminal of said first inverter means and for supplying an address enable digital signal, which is equal to logic 1 when it is desired to enable the digital to analog conversion process for said first digital data signal, from said first digital computer means to the input of said first inverter means;
- means for connecting the output terminal of said first inverter means to the second input terminal of said first OR gate;
- a four bit to ten bit decoder means having first, second, third, and fourth input terminals and first through tenth output terminals;
- means for supplying a four bit digital address signal from said first digital computer means to said first, second, third, and fourth input terminals of said four to ten bit decoder means;
- a plurality of second OR gate means, equivalent to the number of said first data register means, each having first and second input terminals and an output terminal;
- means for connecting the output terminal of said first OR gate means to the first input terminal of said plurality of said second OR gate means;
- means for connecting the second output terminal of said four bit to ten bit decoder to the second input terminal of a first one of said second OR gate means;
- means for connecting the fourth output terminal of said four bit to ten bit decoder to the second input terminal of a second one of said second OR gate means;
- means for connecting the sixth output terminal of said four bit to ten bit decoder to the second input terminal of a third one of said second OR gate means if a third one of said second OR gate means is utilized;
- means for connecting the eighth output terminal of said four bit to ten bit decoder to the second input terminal of a fourth one of said second OR gate means if a fourth one of said second OR gate means is utilized;
- means for connecting the ninth output terminal of said four bit to ten bit decoder to the second input terminal of a fifth one of said second OR gate means if a fifth one of said second OR gate means is utilized;
- means for connecting the tenth output terminal of said four bit to ten bit decoder to the second input terminal of a sixth one of said second OR gate means if a sixth one of said second OR gate means is utilized;
- a plurality of third OR gate means, equivalent to the number of said second OR gate means, each having first and second input terminals and an output terminal;
- means for connecting the output terminal of said first one of said second OR gate means to the first input terminal of a first one of said third OR gate means;
- means for connecting the output terminal of said second one of said second OR gate means to the first input terminal of a second one of said third OR gate means;
- means for connecting the output terminal of said third one of said second OR gate means to the first input terminal of a third one of said third OR gate means if a third one of said second OR gate means is available;
- means for connecting the output terminal of said fourth one of said second OR gate means to the first input terminal of a fourth one of said third OR gate means if a fourth one of said second OR gate means is available;
- means for connecting the output terminal of said fifth one of said second OR gate means to the first input terminal of a fifth one of said third OR gate means if a fifth one of said second OR gate means is available;
- means for connecting the output terminal of said sixth one of said second OR gate means to the first input terminal of a sixth one of said third OR gate means if a sixth one of said second OR gate means is available;
- means for establishing a clock signal;
- second inverter means having an input terminal and an output terminal;
- means for supplying said clock signal to the input terminal of said second inverter means;
- means for connecting the output terminal of said second inverter means to the second input terminal of said plurality of said third OR gate means;
- means for connecting the output terminal of said first one of said third OR gate means to the second input terminal of a first one of said first data register means to enable said first one of said first data register means if the output terminal of said first one of said third OR gate means has a logic value of 0;
- means for connecting the output terminal of said second one of said third OR gate means to the second input terminal of a second one of said first data register means to enable said second one of said first data register means if the output terminal of said second one of said third OR gate means has a logic value of 0;
- means for connecting the output terminal of said third one of said third OR gate means to the second input terminal of a third one of said first data register means to enable said third one of said first data register means if the output terminal of said third one of said third OR gate means has a logic value of 0 if said third one of said first data register means is utilized;
- means for connecting the output terminal of said fourth one of said third OR gate means to the second input terminal of a fourth one of said first data register means to enable said fourth one of said first data register means if the output terminal of said fourth one of said third OR gate means has a logic value of 0 if said fourth one of said first data register means is utilized;
- means for connecting the output terminal of said fifth one of said third OR gate means to the second input terminal of a fifth one of said first data register means to enable said fifth one of said first data register means if the output terminal of said fifth one of said third OR gate means has a logic value of 0 if said fifth one of said first data register means is utilized;
- and
- means for connecting the output terminal of said sixth one of said third OR gate means to the second input terminal of a sixth one of said first data register means to enable said sixth one of said first data register means if the output terminal of said sixth one of said third OR gate means has a logic value of 0 if said sixth one of said first data register means is utilized.
35 more elements
Apparatus comprising:
- a digital computer means for producing a first digital signal and for producing control signals to route said first digital signal to a desired destination;
- a plurality of digital-to-analog converter means, for receiving and converting a digital signal to an analog signal and for supplying said analog signal to a desired destination, each of said plurality of said digital-to-analog converter means having an input terminal and an output terminal;
- a plurality of first data register means, for receiving said first digital signal from said first digital computer means and supplying said first digital signal to at least a respective one of said plurality of said digital-to-analog converter means, each of said plurality of said first data register means having first and second input terminals and an output terminal;
- means for connecting the input terminal of each one of said plurality of said digital-to-analog converter means to the output terminal of a respective one of said plurality of said first data register means;
- means for providing said first digital signal to the first input of said plurality of said first data register means;
- and
- means for automatically selecting one of said plurality of said first data register means to be enabled and for providing a first enabling signal having a predetermined logic value from said first digital computer means to the second input of the selected one of said plurality of said first data register means to enable the selected one of said plurality of said first data register means and initiate the digital-to-analog conversion of said first digital signal;
- a plurality of optical isolator means, for transmitting said first digital signal to a second digital computer means, each of said plurality of said optical isolator means having an input terminal and an output terminal;
- a plurality of voltage-to-current transducer means, each of said transducer means being for receiving a signal output by a respective one of said plurality of said digital-to-analog converter means and for supplying a signal having a desired current level, each of said plurality of said voltage-to-current transducers means having an input terminal and an output terminal;
- means for connecting the input terminal of each one of said plurality of said optical isolator means to the output terminal of a respective one of said plurality of said first data register means;
- means for connecting the output terminal of each of said plurality of said digital-to-analog converter means to a respective one of said plurality of said voltage-to-current transducer means;
- and
- means to initiate the transmission of said first digital signal via one of said plurality of said optical isolator means.
10 more elements
A method for converting an analog signal into a digital signal comprising the steps of:
- establishing a first analog signal;
- establishing an offset voltage signal;
- combining said first analog signal and said offset voltage signal to produce a second analog signal;
- amplifying said second analog signal to thereby establish an amplified second analog signal having a first predetermined relationship to said second analog signal;
- establishing a third analog signal representative of the highest voltage level which is desirable for analog-to-digital conversion;
- comparing said amplified second analog signal to said third analog signal and converting said amplified second analog signal into a first digital signal if the voltage level of said amplified second analog signal does not exceed the voltage level of said third analog signal;
- and
- converting said second analog signal into a first digital signal if the voltage level of said amplified second analog signal exceeds the voltage level of said third analog signal, said offset voltage signal having a voltage level which will reduce the voltage level of said first analog signal to enable said amplified second analog signal to be converted into said first digital signal if the difference between the voltage level of said first analog signal multiplied by the voltage level of said amplified second analog signal divided by the voltage level of said second analog signal, (amplified second/second) and the voltage level of said third analog signal does not exceed the maximum available absolute voltage level of said offset voltage signal multiplied by the voltage level of said amplified second analog signal divided by the voltage level of said second analog signal.
5 more elements
A method for converting a digital signal to an analog signal comprising the steps of:
- establishing a first digital signal;
- establishing control signals to route said first digital signal to a desired destination;
- establishing second digital signal which is equal to logic 0 when said first digital signal is available to be written out to a plurality of first data register means;
- establishing an address enable digital signal which is equal to logic 1 when it is desired to enable the digital-to-analog conversion process for said first digital signal;
- inverting said address enable digital signal;
- establishing a third digital signal which has a logic value of 0 when said second digital signal has a logic value of 0 and said inverted address enable digital signal has a logic value of 0;
- decoding a four bit digital address signal from said digital computer means and supplying first through tenth output signals, each of said first through tenth output signals having a logic value which is determined by the binary value of said four bit digital address signal;
- establishing a fourth digital signal having a logic value of 0 when said first or said third output signals has a logic value of 0;
- establishing a fifth digital signal having a logic value of 0 when said fifth or said seventh output signals has a logic value of 0;
- establishing a sixth digital signal having a logic value of 0 when said fourth digital signal or said fifth digital signal has a logic value of 0;
- establishing a seventh digital signal having a logic value of 0 when said third digital signal and said sixth digital signal have a logic value of 0;
- establishing a clock signal;
- inverting said clock signal;
- establishing an eighth digital signal having a logic value of 0 when said seventh digital signal has a logic value of 0 and said inverted clock signal has a logic value of 0;
- utilizing said eighth digital signal to enable a second data register means;
- transmitting the most significant bits of said first digital signal from said digital computer means and storing the most significant bits of said first digital signal in said second data register means until the least significant bits of said first digital signal have also been transmitted from said digital computer means and then transmitting the combination of the most significant bits and the least significant bits of said first digital signal to the first input terminal of said plurality of said first data register means;
- and
- utilizing the logic sequence of said control signals to automatically select one of said plurality of said first data register means to be enabled and to provide a first enabling signal having a predetermined logic value to the second input of the selected one of said plurality of said first data register means to enable the selected one of said plurality of said first data register means and initiate the digital-to-analog conversion of said first digital signal.
15 more elements
A method for converting a digital signal to an analog signal comprising the steps of:
- establishing a first digital signal;
- establishing control signals to route said first digital signal to a desired destination;
- establishing a second digital signal which is equal to logic 0 when said first digital signal is available to be written out to a plurality of first data register means;
- establishing an address enable digital signal which is equal to logic 1 when it is desired to enable the digital-to-analog conversion process for said first digital signal;
- inverting said address enable digital signal;
- establishing a third digital signal which has a logic value of 0 when said second digital signal has a logic value of 0 and said inverted address enable digital signal has a logic value of 0;
- decoding a first four bit digital address signal from said digital computer means and supplying first through tenth output signals, each of said first through tenth output signals having a logic value which is determined by the binary value of said first four bit digital address signal;
- establishing a fourth digital signal having a logic value of 0 when said third digital signal has a logic value of 0 and the one of said first through tenth output signals tied to a first one of a plurality of cards, each card having a plurality of said first data register means, has a logic value of 0 signifying that said first one of said plurality of cards has been selected;
- decoding a second four bit digital address signal from said digital computer means and supplying eleventh through twentieth output signals each of said eleventh through twentieth output signals having a logic value which is determined by the binary value of said second four bit digital address signal;
- establishing a fifth digital signal having a logic value of 0 when said eleventh or said thirteenth output signals has a logic value of 0;
- establishing a sixth digital signal having a logic value of 0 when said fifteenth or said seventeenth output signals has a logic value of 0;
- establishing a seventh digital signal having a logic value of 0 when said fifth digital signal or said sixth digital signal has a logic value of 0;
- establishing an eighth digital signal having a logic value of 0 when said fourth digital signal and said seventh digital signal have a logic value of 0;
- establishing a clock signal;
- inverting said clock signal;
- establishing a ninth digital signal having a logic value of 0 when said eighth digital signal has a logic value of 0 and when said inverted clock signal has a logic value of 0;
- utilizing said ninth digital signal to enable a second data register means;
- transmitting the most significant bits of said first digital signal from said digital computer means and storing the most significant bits of said first digital signal in said second data register means until the least significant bits of said first digital signal have also been transmitted from said digital computer means and then transmitting the combination of the most significant bits and the least significant bits of said first digital signal to the first input terminal of said plurality of said first data register means on said first one of said cards selected;
- utilizing the logic sequence of said control signals to automatically select one of said plurality of said first data register means to be enabled and to provide a first enabling signal having a predetermined logic value to the second input of the selected one of said plurality of said first data register means to enable the selected one of said plurality of said first data register means and initiate the digital-to-analog conversion of said first digital signal.
16 more elements
A method for converting a digital signal to an analog signal comprising the steps of:
- establishing a first digital signal;
- establishing control signals to route said first digital signal to a desired destingation;
- utilizing the logic sequence of said control signals to provide said first digital signal to the first input of a plurality of first data register means;
- and
- establishing a second digital signal which is equal to logic 0 when said first digital signal is available to be written out to said plurality of said first data register means;
- establishing an address enable digital signal which is equal to logic 1 when it is desired to enable the digital-to-analog conversion process for said first digital data signal;
- inverting said address enable digital signal;
- establishing a third digital signal which has a logic value of 0 when said second digital signal has a logic value of 0 and said inverted address enable digital signal has a logic value of 0;
- decoding a four bit digital address signal from said first digital computer means and supplying first through tenth output signals each of said first through tenth output signals having a logic value which is determined by the binary value of said four bit digital address signal;
- supplying said third digital signal to the first input terminal of a plurality of first OR gate means;
- supplying said second output signal to the second input terminal of a first one of said first OR gate means;
- supplying said fourth output signal to the second output terminal of a second one of said first OR gate means;
- supplying said sixth output signal to the second input terminal of a third one of said first OR gate means if a third one of said first OR gate means is utilized;
- supplying said eighth output signal to the second input terminal of a fourth one of said first OR gate means if a fourth one of said first OR gate means is utilized;
- supplying said ninth output signal to the second input terminal of a fifth one of said first OR gate means if a fifth one of said first OR gate means is utilized;
- supplying said tenth output signal to the second input terminal of a sixth one of said first OR gate means if a sixth one of said first OR gate means is utilized;
- connecting the output terminal of each one of said plurality of said first OR gate means to the first input terminal of a respective one of a plurality of second OR gate means;
- establishing a clock signal;
- inverting said clock signal;
- supplying said inverted clock signal to the second input terminal of said plurality of said second OR gate means;
- connecting the output terminal of a first one of said second OR gate means to the second input terminal of a first one of said first data register means to enable said first one of said first data register means if the output terminal of said first one of said second OR gate means has a logic value of 0;
- utilizing the logic sequence of said control signals to provide said first digital signal to the first input of a plurality of first data register means;
- and
- utilizing the logic sequence of said control signals to automatically select one of said plurality of said first data register means to be enabled and to provide a first enabling signal having a predetermined logic value to the second input of the selected one of said plurality of said first data register means to enable the selected one of said plurality of said first data register means and initiate the digital-to-analog conversion of said first digital signal;
- utilizing the logic sequence of said control signals to initiate transmission of said first digital signal via one of a plurality of optical isolator means;
- and
- converting the analog signal established in the digital-to-analog conversion of said first digital signal from a voltage to a current.
24 more elements
A method for converting a digital signal to an analog signal comprising the steps of:
- establishing a first digital signal;
- establishing control signals to route said first digital signal to a desired destination;
- utilizing the logic sequence of said control signals to provide said first digital signal to the first input of a plurality of first data register means;
- and
- utilizing the logic sequence of said control signals to automatically select one of said plurality of said first data register means to be enabled and to provide a first enabling signal having a predetermined logic value to the second input of the selected one of said plurality of said first data register means to enable the selected one of said plurality of said first data register means and initiate the digital-to-analog conversion of said first digital signal;
- utilizing the logic sequence of said control signals to initiate transmission of said first digital signal via one of a plurality of optical isolator means;
- and
- converting the analog signal established in the digital-to-analog conversion of said first digital signal from a voltage to a current.
5 more elements
Dependencies are inferred from the claim text.