Data transmitter device
AssigneeHochiki Corporation
InventorsKatsuya Yasuda, Akio Adachi
Life of this patent
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Abstract
A data transmission system having a clock pulse generator 1, a plurality of transmitters each including a plurality of switches 7-1 for inputting data, gate circuits 5-1 receiving the outputs of said plurality of switches through one inputs thereof and temporary memory circuits 6-1 for temporarily storing the outputs of the gate circuits. Scanning circuits 3-1 apply outputs successively in synchronization with the output pulses from the clock pulse generator. The transmitters are interconnected first by a synchronous line S.sub.1 adapted to apply the output pulses of the clock pulse generator to the scanning circuits in the transmitters and secondly by a signal line S.sub.2 connecting the outputs terminals of the gate circuits in the transmitters.
Claims15
A data transmission system comprising:
- a clock pulse generator generating output clock pulses, a plurality of transmitters, each transmitter including scanning means receiving clock pulses, a plurality of switches for inputting data, gate circuit means receiving the outputs of said plurality of switches through one input thereof, memory means for temporarily storing the outputs of said gate circuit means, and wherein said scanning means applies output signals to said gate circuit means successively in synchronization with the clock pulses of said clock pulse generator, said transmitters being interconnected first by a synchronous line adapted to apply the output pulses of said clock pulse generator to the scanning means in said plurality of transmitters and secondly by a signal line connecting the output terminals of said gate circuit means in said plurality of transmitters.
A data transmission system comprising:
- a first transmitter including:
- a clock pulse generator;
- a plurality of first switches receiving input data;
- first gate circuits respectively receiving the outputs of said first switches through one input terminal thereof;
- first memory means for temporarily storing the outputs of said first gate circuits;
- first scanning means receiving clock pulses and applying signals to second input terminals of said first gate circuits successively in synchronization with the output pulses of said clock pulse generator;
- means for generating a clear signal having a pulse width is longer than that of the output pulse of said clock pulse signal;
- a second gate circuit receiving the output pulse of said clock pulse generator and the output of said means for generating the clear signal;
- and means for clearing said first scanning means, and
- a plurality of second transmitters each including:
- a plurality of second switches corresponding to data inputted through said first switches;
- third gate circuits receiving the outputs of said second switches at one input terminal thereof;
- second memory means for temporarily storing the outputs of said third gate circuits;
- second scanning means receiving the outputs of said second gate circuits and applying an output signal to second input terminals of said third gate circuits in synchronization with the output pulses of said clock pulse generator;
- and an integrator for integrating the outputs of said second gate circuits to clear said second scanning circuit,
- said first and second transmitters being interconnected first by a synchronous line adapted to input the outputs of said second gate circuits to said transmitters and second by a signal line connecting the output terminals of said first and third gate circuits in said first and said plurality of second transmitters.
Dependencies are inferred from the claim text.