US 4,232,197 A · Processor for a TDMA burst modem

Abstract

The present invention provides a processor for interfacing a TDMA burst modem (40), which transmits and receives bursts of information at high data rates in assigned time slots, and slow speed terminal processing equipment. The present processor comprises circuitry (50) capable of detecting frame or superframe markers in a received sequence and regenerating such markers, after initiation, at the normal interval for such markers despite false alarms or missed marker signals. Other circuitry (53, 57 and 52, 62) causes a memory (48, 56) to directly output a burst of information during an assigned time slot to the modem (40) and directly store received information from modem (40) during a predetermined interval which is designed to start before and end after the expected arrival of an assigned burst. Slower processing equipment is then used to find and process the burst in the stored information.

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Claims11

Dependent claims

A processing arrangement for interfacing a TDMA burst modem and slow speed terminal processing equipment in a communication system which interchanges bursts of information in assigned time slots of a repetitive TDMA communication sequence, each TDMA communication sequence including a sequence marker signal disposed at a predetermined location therein for reception by the burst modem, the processing arrangement comprising:

first means (50) capable of both detecting the sequence marker signals in the repetitive TDMA communication sequence and generating an output signal in response to the detection thereof;
second means (52, 62) capable of generating a window signal for each burst of information within the TDMA communication sequence desired to be processed by the slow speed terminal processing equipment in response to an output signal from the first means
CHARACTERIZED IN THAT
the first means comprises circuitry which also generates an output signal corresponding in time to the normally received sequence marker signals;
the second means generates a window signal which starts at a first predetermined interval and ends at a second predetermined interval from each output signal from the first means, said first and second predetermined interval being scheduled to occur slightly before and slightly after, respectively, the anticipated reception of the desired burst of information;
and
the processing arrangement further comprises
a memory (48, 56) capable of directly storing the portion of the TDMA communication sequence being received during the interval of the window signal generated by the second means in a first section thereof (48) for subsequent detection of the burst information and slow speed processing thereof by the terminal equipment.

5 more elements

An arrangement (50) for detecting and regenerating sequence marker signals received in a predetermined location within a repetitive TDMA communication sequence, the arrangement comprising:

a correlator (100) capable of both detecting when a predetermined plurality of consecutive symbols in both a received TDMA communication sequence and a stored unique word, representative of a sequence marker signal, correspond, and generating an output signal in response to the detection thereof;
lock-on means (110, FIG. 5;
200, 202, 204, 208, 210, 212, 214, 216, FIG. 6) capable of both detecting from the correlator output signals a plurality of y periodic sequence marker signals which are received in y consecutive TDMA communications sequences and generating an output signal in response to the detection thereof;
and
inhibiting means (170, 172, 174, 176, 178, 180, 182, 184, FIG. 5;
204, 216, FIG. 6) comprising first means capable of detecting the failure of the correlator to generate a plurality of z output signals concurrent with the expected reception by the processing arrangement of z consecutive periodic sequence marker signals and generating an output signal in response to the failure detection thereof for inhibiting the output signal of the arrangement
CHARACTERIZED IN THAT
the arrangement further comprises
a sequence marker signal regeneration means (130, FIG. 5;
204, 212, 216, 220, 222, 232, FIG. 6) comprising
an oscillator (136, FIG. 5;
216, FIG. 6) capable of separately generating a continuous sequence of arrangement output signals which have a period corresponding to the period of the expected reception of the periodic sequence marker signals;
and
updating means (140, 150, FIG. 5;
222, 232, 212, FIG. 6) capable of detecting phase differences between the output signals from the lock-on means and said oscillator and generating an output signal capable of altering the phase of said oscillator to eliminate said phase differences;
and
the inhibiting means further comprises
second means (180, 182, FIG. 5;
204, 216, FIG. 6) capable of, during an initiation sequence of the arrangement, causing the output signals from the arrangement to be inhibited until the lock-on means generates a first one of its output signals.

16 more elements

Dependencies are inferred from the claim text.

Description7,547 words

Summary669 words

#The present invention relates to a processor for a time division multiple access (TDMA) burst modem and, more particularly, to a processor for a TDMA burst modem which functions to regenerate marker indications from marker signals received in each frame or superframe signaling format and, in response to such marker indications, enable a high speed memory for directly storing received signals, or for transmitting bursts, during one or more generated window intervals within the frame or superframe period.

#In a time division multiple access (TDMA) satellite communication system, the various ground stations are assigned separate time slots within a frame period for transmitting bursts of information to other ground stations and for receiving bursts of information from other ground stations. In order to transmit or receive bursts of information within the proper assigned time slot of a frame interval, various synchronization and acquisition techniques have been proposed.

#For example, in U.S. Pat. No. 3,643,031, issued to H. Sasaki et al on Feb. 15, 1972, a burst synchronization control unit is disclosed wherein counters count the frame periods to forecast the reception in the next frame period and a unique word detecting circuit then provides station discrimination from control information included in each received burst.

Brief description of the drawings9 figures

#Referring now to the drawings, in which like numerals represent like parts in the several views:

#FIG. 1 is a block schematic of a prior art satellite time-division interconnection arrangement for selectively interconnecting a plurality of fixed up-link spot beams and an up-link scanning spot beam with a plurality of fixed down-link spot beams and a down-link scanning spot beam;

#FIG. 2 illustrates an exemplary prior art switching frame sequence format for concurrently interconnecting 11 up-link fixed spot beams and one up-link scanning spot beam with 11 down-link fixed spot beams and one down-link scanning spot beam for use with the arrangement of FIG. 1;

Detailed description6,605 words

#FIG. 1 illustrates a prior art basic satellite switching repeater 10 configuration for concurrently transmitting and receiving a plurality of fixed spot beams and one scanning spot beam. Such configuration is being described only to provide background information to permit subsequent illustration of how the present processor may operate in ground stations associated with either fixed or scanning spot beams in systems which may employ either fixed or scanning spot beams or both. For illustrative purposes hereinafter only, 11 up-link and 11 down-link fixed spot beams designated 12a-12k and 13a-13k, respectively, and a scanning up-link and down-link spot beam designated 14 and 15, respectively, are shown. Each of the associated up-link and down-link fixed spot beams 12a, 13a; 12b, 13b; . . . ; 12k, 13k are received from and transmitted to a separate fixed geographical ground areas (not shown) within the viewing area of satellite switching repeater 10. The up-link and down-link scanning spot beams 14 and 15 are scanned independently among a plurality of spaced-apart geographical ground areas (not shown) which do not form a part of the geographical ground areas associated with the various fixed spot beams 12 and 13. For illustrative purposes hereinafter only, the plurality of corresponding spaced-apart geographical ground areas associated with scanning spot beams 14 and 15 will be considered to include one hundred separate areas. It is also to be understood that each of the 11 fixed spot beam and 100 scanning spot beam geographical ground areas can include one or more ground stations desiring to communicate with any of the other ground stations in the same or other geographical ground areas.

#Each of the up-link fixed spot beams 12a-12k are shown being intercepted or received at antennas 16a-16k, respectively, while each of the down-link fixed spot beams 13a-13k, are launched by antennas 17a-17k, respectively. The up-link and down-link scanning spot beams 14 and 15 are respectively received and transmitted by, for example, a phase array antenna as shown in FIG. 1 where the up-link receiving array and down-link transmitting array are each shown as comprising a plurality of m elementss 18.sub.1 -18.sub.m and 19.sub.1 -19.sub.m, respectively. The receiving antenna elements 18.sub.1 -18.sub.m are connected to phase shifters 20.sub.1 -20.sub.m, respectively, which, in turn, are connected to a summing circuit 21 for combining the output signals from phase shifter circuits 20.sub.1 -20.sub.m into a single combined output signal on lead 22. Similarly, the input terminal of the down-link transmitting antenna elements 19.sub.1 -19.sub.m are connected to the output terminals of phase shifters 23.sub.1 -23.sub.m, respectively, with the input terminal of phase shifters 23.sub.1 -23.sub.m being connected to the output terminals of a splitting circuit 24. Splitting circuit 24 receives the instantaneous signal to be transmitted via scanning spot beam 15 on lead 25 and divides the signal equally for distribution to phase shifters 23.sub.1 -23.sub.m which alters the phase of the associated input signal in a manner to cause elements 19.sub.1 -19.sub.m to transmit scanning spot beam 15 in the desired direction as is well known in the art.

#In the operation of each of scanning spot beams 14 and 15, an array processor 26 transmits a sequence of control signals over a bus 27 to each of the up-link phase shifters 20.sub.1 -20.sub.m to cause the array to scan spot beam 14 over the associated scanning spot beam geographical ground areas in synchronization with the expected reception of signals from such ground areas. Concurrent therewith, the array processor 26 similarly transmits a separate sequence of control signals over a base 28 to each of the down-link phase shifters 23.sub.1 -23.sub.m to cause the array to scan spot beam 15 over the associated scanning spot beam geographical ground areas in synchronization with the expected transmission of signals to such areas.

Processor for a TDMA burst modem

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Processor for a TDMA burst modem

Life of this patent

Life of this patent

Abstract

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Claims11

Description7,547 words

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Classification2 codes

Life of this patent

Description7,547 words