Dielectric isolation method using shallow oxide and polycrystalline silicon utilizing a preliminary etching step
AssigneeMassachusetts Institute of Technology
InventorsJack I. Raffel, Stephen E. Bernacki
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AssigneeMassachusetts Institute of Technology
InventorsJack I. Raffel, Stephen E. Bernacki
Estimating the term…
A process is described which combines polycrystalline isolation of collectors and shallow oxide isolation of bases. This approach is capable of providing deep dielectric isolation, surface planarity and the high density of walled emitter geometries, a combination heretofore unobtainable by any other means. This isolation scheme has been used to fabricate ECL gate chains. The transistors were located in 2.5 micron thick n epi islands surrounded by 5.times.10.sup.5 ohm-cm polysilicon selectively oxidized with silicon nitride masking to a thickness of one micron. The oxide "bump" at the nitride mask was typically 3000 A and the epi-poly step height was as small as 2600 A. The circuits have polysilicon resistors and were fabricated using both thermal diffusion and ion implantation. The power-delay product of these circuits was approximately one-half that of junction isolated circuits.
A method for achieving isolation of the silicon islands of integrated circuits comprising:
Dependencies are inferred from the claim text.