Variable thickness self-aligned photoresist process

In the fabrication of integrated circuits, a process for forming a photoresist layer having two thicknesses comprising the steps of:

• providing a masking member having first areas which freely pass light, second areas which are substantially opaque and third areas comprising spaced apart features of predetermined dimensions and spacing;
• projecting light through said masking member onto said photoresist layer with a projection apparatus, said apparatus being unable to optically resolve the image of said third areas, such that the portion of said layer receiving light passing through said third areas is illuminated at an intermediate intensity;
• and
• developing said photoresist layer;
• whereby two different thicknesses of said layer are formed with a single masking step.

In the fabrication of integrated circuits, a process for forming a photoresist layer having two thicknesses comprising the steps of:

• providing a masking member having first areas which freely pass light, second areas which are substantially opaque and third areas which partially pass light;
• projecting light onto a photoresist layer with a projection apparatus such that first regions of said photoresist layer which receive light from said first areas of said masking member are fully exposed, second regions of said photoresist layer which receive light from said second areas of said masking member are substantially unexposed, and third regions of said photoresist layer which receive light from said third areas of said masking member are illuminated at an intermediate intensity;
• and
• developing said photoresist layer;
• whereby two different thicknesses of said layer are formed with a single masking step.

A process for forming a doped region in a substrate spaced-apart from a polysilicon gate member by a predetermined distance comprising the steps of:

• forming a polysilicon layer above said substrate;
• forming a photoresist layer over said polysilicon layer;
• exposing said photoresist layer to a masking member which includes a first area which substantially blocks light, a second area adjacent to said first are a having a width corresponding to said predetermined distance, said second area comprising a plurality of lines of preselected width and spacing and a third area adjacent to said second area which freely passes light;
• projecting light with a projection apparatus through said masking member to expose said photoresist layer, said projection apparatus having a maximum resolution less than that required to project said lines;
• developing said photoresist layer to form a first region of a first thickness, a second region of a second thickness, said second thickness being less than said first thickness, said first and second regions corresponding to said first and second areas, respectively, of said masking member;
• doping said substrate employing said photoresist layer as a mask to form said doped region, said doped region being formed in alignment with said second region of said photoresist layer;
• etching said photoresist layer so as to remove a thickness of photoresist approximately equal to said second thickness;
• and
• etching said polysilicon layer using said first region of said photoresist layer as a mask to form said gate member;
• whereby said doped region is spaced-apart from said gate member by said predetermined distance.