Semiconductor integrated circuit device
AssigneesNippon Telegraph & Telephone Public Corporation, Fujitsu Limited
InventorsMasao Suzuki, Toshio Hayashi, Kuniyasu Kawarada, Kazuhiro Toyoda, Chikai Ono
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Abstract
An improved semiconductor integrated circuit device having a memory cell array formed of integrated injection logic memory cells. The semiconductor integrated circuit according to the present invention includes integration injection logic memory cells which are arranged in matrix form, word lines and bit lines which are connected to the memory cells arranged in the row or column directions, one of the word lines being formed by a semiconductor bulk, current sources provided at least at both ends of the word lines or the bit lines.
Claims9
A semiconductor integrated circuit device having an array of integrated injection logic memory cells, each said integrated injection logic memory cell comprising a pair of first and second transistors of first conduction type with common emitters forming an injector connected to a first word line, a pair of third and fourth transistors of second conduction type having their collectors connected to the collectors of said first and second transistors, respectively, the base of said third transistor being connected to said collector of said fourth transistor and the base of said fourth transistor being connected to said collector of said third transistor, said first and second transistors having bases connected in common to emitters of said third and fourth transistors and to a second word line, said second word line thusly connecting to each said memory cell of said at least one array, said semiconductor integrated circuit device comprising
- a bulk of said semiconductor device forming said second word line,
- at least two current sources connected in a distributed fashion to said second word line of said memory cell array.
Dependencies are inferred from the claim text.