Cordic FFT processor
AssigneeRaytheon Company
InventorsPaul C. Barr, Herbert L. Groginsky
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Abstract
An apparatus for performing a Fourier transform using Cordic techniques. Digital words are pipelined through serial add/subtract stages to provide vector rotations without trignometric lookup tables or multiply operations. The throughput of an FFT butterfly calculation is increased over prior art digital processors. A plurality of apparatus may be pipelined in a system to further increase the throughput rate. Also, the apparatus may be programmed to perform vector rotations through a plurality of angles thus providing the capability to compute FFT's of varying numbers of points.
Claims9
In combination:
- a plurality of pairs of arithmetic elements adapted for input of two digital words, each of said elements providing as an output either a sum or difference of two input digital words;
- a storage means connected to the output of each of said elements;
- means for connecting said pairs of elements and storage means in a series, said connecting means hardwire connecting bits of the contents of storage means to inputs of both of the elements of the next sequential pair of elements in said series;
- and
- said connecting means comprising means for bit transpositioning where necessary such that if the contents of two said storage means of a pair of elements are X.sub.i and Y.sub.i where i is the number of the arithmetic element pair in said series, the outputs of the next sequential pair of arithmetic elements in said series will be X.sub.i .+-.2.sup.i Y.sub.i and Y.sub.i .+-.2.sup.-i X.sub.1, respectively.
A system for performing a Fourier transform comprising:
- a plurality of computational stages, each stage comprising means for performing arithmetic add and subtract operations on a pair of input digital words and means for storing the results of said operations;
- means for coupling said storing means of one stage to the next sequential stage of said series, said coupling means comprising means for hardwire connecting bits of the contents of said storing means of said one stage to inputs of both of said elements in said next sequential stage, said connecting means comprising means for bit transpositioning as required such that if the contents in said storing means of one stage are respectively X.sub.i and Y.sub.i where i is the number of the stage in the series, the coupled inputs to the next sequential stage are X.sub.i, Y.sub.i, 2.sup.-i X.sub.i and 2.sup.-i Y.sub.i ;
- and
- means for clocking pairs of digital word inputs through said stages.
Dependencies are inferred from the claim text.