Microprocessor support system

A processor support system for providing hardware debugging and software development capabilities for an application system which contains both a memory device and an application processor which processor drives data, address, and control buses of said application system, wherein said microprocessor support system comprises:

• computer means responsive to control signals input from a user terminal for running an operating system to generate control instructions and to manipulate data;
• field test unit means connected to said computer means by a data link and directly connected to said application system for ordering the flow of said data between said computer means and said application system;
• wherein said field test unit means includes:
• field test unit data, address, and control bus means for interconnecting the various circuits of said field test unit means;
• program store means connected to said field test unit data, address, and control bus means for storing said control instructions generated by said computer means to regulate the operation of said field test unit means;
• data receiver means connected to both said data link and said field test unit data, address, and control bus means, wherein said data receiver means are responsive to said computer means transmitting said control instructions to said field test unit means via said data link for writing said control instructions into said program store means via said field test unit data, address, and control bus means;
• processor means connected to said field test unit data, address, and control bus means and responsive to said control instructions stored in said program store means for driving said field test unit data, address, and control bus means;
• memory means connected to said field test unit data, address, and control bus means for storing data generated by said application system;
• interface means connected to said field test unit data, address, and control bus means and directly connectable to said application system data, address, and control buses for providing bidirectional data transfer between said application system data, address, and control buses and said memory means via said field test unit data, address, and control bus means in response to control signals transmitted to said processor means to said interface means via said field test unit data, address, and control bus means;
• and
• data transmission means connected to both said data link and said field test unit data, address, and control bus means and responsive to said processor means for transmitting said data from said memory means to said computer via said data link.