Data transfer system

A data transfer system comprising:

• a central processor;
• a plurality of peripheral equipments;
• and
• a group of buses including an address bus, a data bus and a status bus, said group of buses being provided between said central processor and said peripheral equipments;
• at least one of said peripheral equipments having at least two data receiving registers while the remaining peripheral equipments have one data receiving register, the number of data receiving registers being determined by the operating requirements of each peripheral equipment,
• said central processor operatively fetching and executing an instruction which indicates data transfer to one of the peripheral equipments and includes an operation command and an address information designating the selected one peripheral equipment, said central processor having a plurality of data registers for storing data to be transferred, the total sum of data storing capacity of said data storing registers corresponding to the maximum total sum of data receiving capacity of said receiving registers of said at least one peripheral equipment, an instruction register for latching the instruction read out of a main memory designating data transfer to one of the peripheral equipments, said instruction including an address command designating the address information of said selected one peripheral equipment and an operation command, first means for decoding the address command and for transmitting to said address bus the thus decoded address information, second means for decoding the operation command, a plurality of gates one of the gates being provided for each one of the data registers and the plurality of gates being rendered operative one after another in response to a gate operation control signal supplied thereto for enabling transmission to said data bus data stored in the data register associated with the operative one of the gates, executing means supplied with the thus decoded operation command from said second means for generating control signals in timed sequence in accordance with a prescribed program which is predetermined by the operation command, said timed sequence generated control signals being supplied to the plurality of gates as the gate operation control signal thereof, and means for terminating the operation of the executing means, and
• each of said peripheral equipments further having means connected to the address bus to receive the address information transmitted therethrough for judging whether or not the address information designates the associated peripheral equipment, means for permitting receipt of data transmitted through the data bus into the associated receiving registers when the judging means judges the associated peripheral equipment is selected, and status signal means for judging whether or not all of the required data is fully received by the associated receiving registers and for generating a status signal indicating that the data is not fully received by the associated receiving registers, so that said status signal means transmits the status signal to the status bus for permitting transmission to said central processor,
• said executing means being responsive to the status signal transmitted through the status bus for maintaining generation of the control signals so as to permit transmitting to the data bus data stored in another of said data registers, and
• said terminating means being responsive to the absence of the status signal on the status bus for terminating the generation of the control signal by said executing means,
• whereby transmission request of data transfer is initiated from each selected one of the peripheral equipments without changing the same instruction latched by the instruction register.