US 4,230,958 A · Loss of clock detector circuit

Abstract

This invention involves a detector circuit in MOS technology for sensing "loss of clock"; that is, whenever a clock input voltage pulse source is interrupted or stops (becomes "stuck") at any level, the output voltage of the detector circuit is at a high level, but is at a low level when the clock is working properly. Such a circuit is achieved by means of a first MOS electrical inverter (I.sub.1), connected for feeding its output to an MOS electrical differentiator (.DELTA.), connector for feeding its output to a thresholding MOS amplifier (A), connected for feeding its output to a unidirectional MOS current inhibitor (D), connected for feeding its output to a second MOS electrical inverter (I.sub.2), connected in parallel with a storage capacitor (C) in parallel with a leakage current source (J.sub.L), whereby the output of the second inverter is a binary indication of the presence vs. absence of clock pulse input to the first inverter.

Claims9

Dependent claims

Semiconductor apparatus comprising:

(a) an MOS differentiator (.DELTA.) having an input terminal;
(b) an MOS thresholding amplifier (A) having an input terminal connected to an output terminal of the differentiator (.DELTA.);
(c) an MOS unidirectional current inhibitor (D) having an input terminal connected to an output terminal of the amplifier (A);
(d) an MOS storage capacitor (C) having one terminal connected to an output terminal of the inhibitor (D);
(e) a leakage current source (J.sub.L) connected to said one terminal for providing a leakage current thereto if and only if the charge on said terminal is above a threshold, said inhibitor (D) directed for delivering charge in a direction tending to charge said one terminal and said leakage current being in a direction tending to discharge said one terminal;
whereby the voltage level at said one terminal is a binary indication of whether or not clock pulse voltage is being applied to the input terminal of the differentiator (.DELTA.).

3 more elements

Semiconductor apparatus comprising:

(a) a first MS transistor (T.sub.1) whose source is connected to a first node N.sub.1 ;
(b) a second MOS transistor (T.sub.2), characterized by a high transconductance at least ten times that of the first transistor (T.sub.1), the drain of T.sub.2 being connected to said first node (N.sub.1), and the gate electrode of T.sub.2 being connected to an input node (N.sub.2);
(c) a third MOS transistor (T.sub.3) whose source is connected to its drain and whose gate electrode is connected to the first node (N.sub.1);
(d) a fourth MOS transistor (T.sub.4), characterized in its "on" state by a fourth impedance, whose drain is connected to the drain of the third transistor (T.sub.3);
(e) a fifth MOS transistor (T.sub.5) whose gate electrode is connected to the drain of the fourth transistor (T.sub.4);
(f) a sixth MOS transistor (T.sub.6) whose source is connected to the drain of the fifth transistor (T.sub.5), the transconductance of T.sub.5 being at least ten times that of T.sub.6 ;
(g) a seventh MOS transistor (T.sub.7) whose source is connected to the drain of an eighth MOS transistor (T.sub.8), the gate electrode of said eighth transistor being connected to the drain of the fifth transistor (T.sub.5), the transconductance of T.sub.8 being at least ten times that of T.sub.7 ;
(h) a ninth MOS transistor (T.sub.9) whose gate electrode is connected to its drain and to the drain of the eighth transistor (T.sub.8);
(i) a tenth MOS transistor (T.sub.10) whose drain is connected to the source of the ninth transistor (T.sub.9) and whose gate electrode is connected to the drain of an eleventh MOS transistor (T.sub.11) and to the source of a twelfth MOS transistor (T.sub.12), the transconductance of T.sub.11 being at least ten times that of T.sub.12 ;
(j) a thirteenth MOS transistor (T.sub.13) whose source is connected to its drain and whose gate electrode is connected to the drain of the tenth transistor (T.sub.10).

7 more elements

Dependencies are inferred from the claim text.

Loss of clock detector circuit

Life of this patent

Loss of clock detector circuit

Life of this patent

Abstract

Claims9