Logic JK flip-flop structure

A logic bistable JK flip-flop structure capable of being realized in integrated circuit technology with complementary MOS transistors, comprising at least three logic gates each of which comprises a first group of transistors of a first conduction type and a second group of transistors of a second conduction type, these two groups of transistors being connected in series across the terminals of a voltage supply source and their common connection point forming the output node of the gate, the conduction paths of the transistors of each group being connected in series and/or in parallel with each other, so that the conduction state of these transistors define the potential at the output node of the gate, which represents the inner variable provided by this gate and may take values substantially equal to those at the two terminals of the voltage supply source, each transistor being controlled by an inner variable or by an external control variable such as J, K or H, H being a clock signal, the said structure comprising the following logic gates, respectively indicated by the inner variable they provide, said gates being formed by transistors indicated for each group and designated by their respective control variables, the connection of the conduction paths of these transistors being indicated in each group by "series" or "parallel", an assembly indicated between brackets being considered as a whole:

• Gate A:
• first group:
• (B series J) parallel (C series H)
• second group:
• (B parallel J) series H
• Gate B:
• first group:
• A series H
• second group:
• A
• Gate C:
• first group:
• A series (B parallel K)
• second group:
• (B series K series H) parallel A,
• the transistor controlled by A in the first groups of the gates B and C being preferably common to these gates and the output variable Q of the circuit being the variable B.