Energy compensation means for digital cardiac pacemaker

In a digital cardiac pacemaker pulse generator for providing cardiac stimulating pulses having clock means for providing a series of clock pulses at a fixed frequency;

• counter means responsive to said clock means for counting said clock pulses;
• decoding means responsive to the count of said counter means for providing signals upon said counter means reaching certain counts manifesting the leading and trailing edges of said cardiac stimulating pulses;
• battery means for providing a decreasing magnitude of voltage over an extended period of time;
• and output means for providing said cardiac stimulating pulses in response to said decoding means, said cardiac stimulating pulses having a voltage related to said battery voltage;
• the improvement of apparatus for providing cardiac stimulating pulses of increasing pulse width as said battery voltage decreases comprising:
• voltage control oscillator means for providing a series of pulses at a frequency proportional to the magnitude of said voltage;
• and
• gate means for providing said voltage controlled oscillator pulses to said counter means between said leading and trailing edges of said cardiac stimulating pulses and for providing said clock means pulses to said counter means between the trailing and leading edges of said cardiac stimulating pulses.

A digital cardiac pacemaker pulse generator for providing cardiac stimulating pulses to output terminals adapted to having lead means coupled thereto, said pulse generator being powered by battery having a characteristic that the voltage provided thereby decreases with time, said cardiac stimulating pulse having a voltage magnitude related to the voltage provided by said battery, said pulse generator comprising:

• crystal controlled oscillator means for providing a chain of clock pulses at a stable frequency;
• voltage controlled oscillator means for providng a chain of clock pulses at a frequency directly related to the battery voltage;
• first resettable counter means responsive to the application thereto of clock pulses for counting each pulse applied and responsive to a first reset signal for being reset to an initial count;
• counter interface means for providing said first reset signal in response to said first counter means reaching a first count;
• second resettable counter means responsive to the application thereto of said first reset signal for counting each first reset signal;
• rate decoding means responsive to said second counter means reaching a second count for providing a signal manifesting that a cardiac stimulating pulse is to be provided;
• and
• gate means responsive to said rate decoding means signal, said crystal controlled oscillator clock pulses and said voltage controlled oscillator clock pulses for providng said voltage controlled oscillator clock pulses to said first counter means from a time after said rate decoding means signal occurs until said first counter achieves a third count and for providing said crystal controlled oscillator pulses to said first counter means at other times.