Synchronizing circuit for a digital arrangement

A circuit for synchronizing a digital arrangement with an external clock pulse signal, the digital arrangement having a calculating unit receiving during each one of its cycles to be synchronized with the external clock pulse signal both an external information to be entered into a buffer store and, thereafter, a sequence of coefficients originating in a predetermined order from a circulating store formed by a number of shift registers equal to the number of coefficients, these shift registers being shifted by pulses derived from a main clock generator, said synchronizing circuit comprising:

• switching means included in said circulating store for having the coefficients circulate in series in the cascade-connected registers, word by word, each coefficient being one word length;
• means for deriving from said main clock generator a word clock corresponding to the duration of circulation of a coefficient in a register;
• means for forming in synchronism with the word clock, operating cycles of constant duration for said calculating unit and a read signal for said buffer store at the beginning of each cycle;
• a transition detection circuit to start each cycle arranged for detecting at the occurrence of a word clock pulse the characteristic transition of the external clock pulse signal appearing after the end of each cycle;
• said switching means being controlled so that said coefficients circulate word-by-word from the end of each cycle to the instant at which within the next cycle said buffer store has been read and that thereafter said sequence of coefficients circulates in series until the end of said next cycle.