Digital clock phase recovery circuits for data receiver
AssigneeBell Telephone Laboratories, Incorporated
InventorsDavid J. Thomson, Roland J. Turner
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Abstract
To stabilize the phase of bit rate clock signals recovered from a self-clocking data signal, e.g., a Manchester coded signal, extra signal level transition pulses (58) occurring during intervals of successive bits of the same info bit type are inverted (59) to reinforce the desired phase of the bit-rate frequency component.
Claims6
In a data transmission system for data signals in which there is in each data bit time at least one signal transition between binary information signal levels in a direction that is indicative of the data information bit state, and circuits are provided for recovering from the data signals bit clock phase information, the method for deriving that bit clock phase information which includes the steps of
- generating a pulse of a single predetermined polarity in response to each data signal level transition in either direction between binary signal level states and thereby producing a train of unipolar pulses having a bit-rate frequency component,
- sampling said train periodically approximately midway between information-state-representative transition times, and
- reversing the excursion direction in the train of any pulse detected in the sampling step for thereby reinforcing the phase of the bit rate frequency component of the train.
In a signal transmission system wherein self-synchronizing data signals are transmitted, a circuit (39) for deriving phase information from the data and including means (53, 57, 58) for producing a pulse of predetermined polarity in response to each data signal level transition in either direction, the improvement comprising
- means (59) for inverting the excursion direction of any of said pulses occurring approximately at a time edge of a bit interval.
Dependencies are inferred from the claim text.