Full duplex bit synchronous data rate buffer

A communication system (15, 18) for bidirectional transmission of high frequency burst data signals between a first apparatus (1) and a third apparatus (Sn) over low frequency telephone transmission facilities (16, 17) said high frequency signals having an average bit rate lower than the average bit rate of said low frequency telephone facility, said system including

• a data rate buffer (15) for bidirectionally communicating with said first apparatus (1) utilizing high frequency burst data signals, said data rate buffer (15) arranged for converting said high frequency burst signals to low speed data signals for communications over said low frequency telephone facilities (16, 17), and arranged for converting said low frequency data signals received over said telephone facilities (16, 17) to high speed burst data signals,
• a second apparatus (18) for communicating with said data rate buffer (15) at said low frequency signal rate over said telephone facilities (16, 17), said second apparatus (18) arranged for interfacing said low frequency signals with signals of said third apparatus (Sn),
• said data buffer (15) including
• a buffer circuit (101, 102) for converting a first high frequency signal (107) to a first low frequency signal (109), and for converting a second low frequency signal (108) to a second high frequency signal (106),
• characterized in that
• there is provided a buffer control circuit (201-205, 105) for interactively controlling said buffer circuit, said buffer control circuit comprising
• a first synchronizing circuit (201, 105) for bit synchronizing the transmission of each said second high frequency signal (106) from said buffer circuit (101, 102) to said first apparatus (1) with the reception of bits of said first high frequency signal (107) by said buffer circuit (101, 102) from said first apparatus (1), and
• alignment logic (105) for adjusting the number of bits in said second high frequency signal (106) transmitted from said buffer circuit (101, 102) to said first apparatus (1) to be equal to the number of bits in said first high frequency signal (107) received by said buffer circuit (101, 102) from said first apparatus (1), said number of bits of said second high frequency signal (106) being adjustable without affecting said bit synchronism of said data rate buffer (15) with said first apparatus (1).

A bidirectional data rate buffer (15) for interfacing apparatus (1) which utilizes bidirectional high frequency burst data signals (106, 107) with apparatus (18) which utilizes bidirectional low frequency data signals (108, 109), said high frequency data signals (106, 107) having an average data rate lower than the data rate of said low frequency data signals (108, 109) said data buffer (15) including

• a buffer circuit (101, 102) for converting a first high frequency signal (107) to a first low frequency signal (109), and for converting a second low frequency signal (108) to a second high frequency signal (106),
• characterized in that
• there is provided a buffer control circuit (201-205, 105) for interactively controlling said buffer circuit, said buffer control circuit comprising
• a first synchronizing circuit (201, 105) for bit synchronizing the transmission of each said second high frequency signal (106) from said buffer circuit (101, 102) to said first apparatus (1) with the reception of bits of said first high frequency signal (107) by said buffer circuit (101, 102) from said first apparatus (1), and
• alignment logic (105) for adjusting the number of bits in said second high frequency signal (106) transmitted from said buffer circuit (101, 102) to said first apparatus (1) to be equal to the number of bits in said first high frequency signal (107) received by said buffer circuit (101, 102) from said first apparatus (1), said number of bits of said second high frequency signal (106) being adjustable without affecting said bit synchronism of said data rate buffer (15) with said first apparatus (1).

A data rate buffer (15) for both receiving a first high frequency data signal for conversion to a transmitted preselected first low frequency signal, and for transmitting a second high frequency signal from a converted received preselected second low frequency signal, said first and second high frequency signals being identical in frequency and said first and second low frequency signal being identical in frequency, said data rate of said high frequency signals being less than data rate of said low frequency signal over a frame period, said converter including a memory (101, 102) having a storage capacity at least as great as the amount of high frequency or low frequency data received in said frame period

• characterized in that
• there is provided a buffer control circuit (201-205, 105) for controlling said buffer (101, 102) said control circuit (201-205, 105) including
• a first phase regulating circuit for synchronizing the phase of transmitted said second high frequency signal with received said first high frequency signal, and
• an adjusting circuit (105) for adjusting the bit length of transmitted said second high frequency signal to be equal to received said first high frequency signal.