I.sup.2 L Full adder and ALU

A full adder comprising:

• data input means for receiving first and second binary data bits, and for providing the logical complements of the received first and second data bits;
• carry input means for receiving the logical complement of a binary carry-in bit, and for providing the logical complement of the received complement, the result being the carry-in bit;
• NOR logic means connected to the data input means, the NOR logic means receiving the complements of the first and second data bits, and providing the logical AND of the received complements, the result being the logical NOR of the first and second data bits;
• first inverter means connected to the data input means, the first inverter means receiving the complements of the first and second data bits, and providing the logical complement of the received complements, the result being the first and second data bits;
• AND logic means connected to the first inverter means, the AND logic means receiving the first and second data bits, and providing the logical AND of the received first and second data bits;
• second inverter means connected to the AND logic means, the second inverter means receiving the logical AND of the first and second data bits, and providing the logical complement of the received logical AND, the result being the logical NAND of the first and second data bits;
• third inverter means connected to the NOR logic means, the third inverter means receiving the logical NOR of the first and second data bits, and providing the logical complement of the received logical NOR, the result being the logical OR of the first and second data bits;
• XOR logic means connected to the second and the third inverter means, the XOR logic means receiving the logical NAND and the logical OR of the first and second data bits, and providing the logical AND of the received logical NAND and logical OR of the first and second data bits, the result being the logical XOR of the first and second data bits;
• first intermediate logic means connected to the carry input means and to the XOR logic means, the first intermediate logic means receiving the carry-in bit and the logical XOR of the first and second data bits, and providing the logical AND of the received carry-in bit and logical XOR;
• fourth inverter means connected to the carry input means, the fourth inverter means receiving the carry-in bit, and providing the logical complement of the received carry-in bit;
• fifth inverter means connected to the XOR logic means, the fifth inverter means receiving the logical XOR of the first and second data bits, and providing the logical complement of the received logical XOR;
• second intermediate logic means connected to the fourth and fifth inverter means, the second intermediate logic means receiving the logical complements of the carry-in bit and of the logical XOR, and providing the logical AND of the received logical complements;
• sum logic means connected to the first and second intermediate logic means, the sum logic means receiving the logical AND provided by each of the first and second intermediate logic means, determining the logical complement of each received logical AND, and providing the logical AND of the resultant logical complements, the result being the logical sum of the first and second data bits;
• and
• carry output means connected to the carry input means and to the second and third inverter means, the carry output means receiving the carry-in bit and the logical NAND and the logical OR of the first and second data bits, determining the logical NAND of the received carry-in bit and logical OR, and providing the logical AND of the received logical NAND and the determined logical NAND, the result being the carry-out bit from the arithmetic sum of the first and second data bits and the carry-in bit.