US 4,229,792 A · Bus allocation synchronization system

Abstract

An improved bus allocation system to control a time division multiplexed digital data bus used by a plurality of signal sources such as a number of digital processing components in a decentralized system in which there is no single entity controlling the bus. The system includes a mechanism for maintaining allocation synchronization under realistic, non-ideal conditions in which noise or other error producing interferences may be present. Each signal source is provided with a bus interface unit having an address counter which operates in conjunction with an allocation vector. The counters operate through a repeating cycle of counts and one or more of the counts in each cycle based on its allocation vector. Each address counter is synchronized during or following the receipt of a message using a unique comparison sequence of comparisons. By means of this system the value of all counters within the range of synchronization are made identical in response to a bus allocation synchronization signal. If a given address counter is off too many counts to be synchronized, the transmitter of the associated device is disabled until it can be re-synchronized by a later synchronization signal. Thus any device having a counter that is out of synchronization for any reason cannot transmit until such synchronization is restored. This prevents interference occasioned by more than one device using the bus at a given time.

Claims5

Dependent claims

A decentralized bus allocation synchronization system for a plurality of inter-communicating processing devices which share a common data bus in a time multiplexed fashion wherein no single entity controls access to the bus or synchronization of access to the bus comprising:

a plurality of processing devices adapted to communicate along a common bus;
a bus interface unit associated with each of said processing devices for controlling the access of that device to said bus, each said bus interface unit further comprising
transmitting means for transmitting signals over said bus;
receiving means for receiving signals from said bus;
enabling means for enabling access to said bus, said enabling means further comprising:
allocation vector means for storing a predetermined control schedule sequence of instructions related to the use of the bus;
recyclable indexing interface means for indexably addressing said sequence of instructions wherein said indexing is responsive to a command received from said bus;
synchronization checking means for utilizing allocation and synchronization information from previously received communications and the current communication received by said receiving means, and from said indexing interface means to determine the synchronization state of said enabling means;
disabling means for disabling said transmitting means if said synchronization checking means fails to determine synchronization state;
synchronization re-establishing means for re-enabling said transmitter by re-establishing synchronization of said indexing interface means.

7 more elements

A bus allocation synchronization system for use wherein a plurality of inter-communicating processing devices share a common data bus in a time-multiplexed fashion and wherein no single entity controls access to use the bus or synchronization for access to use the bus, said access and synchronization being independently determined by a bus interface unit associated with each of said devices, each of said bus interface units comprising:

transmitting means for transmitting signals over said bus;
receiving means for receiving signals from said bus;
allocation vector means for storing a predetermined control schedule sequence of instructions related to the use of the bus;
recyclable indexing interface means for indexably addressing said sequence of instructions wherein said indexing is responsive to a reallocation command received from said bus;
storage means for storing the value of a source time slot received by said receiving means as part of the current communication from said bus, the current time slot as indicated by said indexing interface means and the old source time slot from a previous communication on said bus received by said received means;
means for comparing the value of the source time slot received with each message with the value of said current time slot, said current time slot plus one and said old source time slot;
means connected to said indexing interface means and said storge means for modifying the value of the current time slot such that when an equality is found for any of said comparisons made by said means for comparing, the value of said current time slot is made to equal said source time slot;
means for disabling said transmitting means when none of the said comparisons are equal;
means connected to said storage means for modifying the value of said old source time slot such that it equals said source time slot received with a message;
means for incrementing the address of said indexing interface means, the value of said current time slot and the value of said old source time slot on reallocation command;
and
means responsive to the values of said time slots for selectively recycling said indexing interface means and the contents of said storage means.

9 more elements

Dependencies are inferred from the claim text.

Bus allocation synchronization system

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Bus allocation synchronization system

Life of this patent

Abstract

Claims5