Concurrent task and instruction processor and method

A concurrent task and instruction processing device, comprising:

• a plurality of task first-in first-out buffers each of which is adapted to receive process data word pointers for storage therein;
• snapshot circuitry connected with task first-in, first-out buffers to sequentially withdraw said pointers therefrom and provide indications thereof;
• a process status word memory connected with said snapshot circuitry to receive said pointers therefrom and responsive thereto coupling process status words from said process status memory;
• a task status word memory connected with said snapshot circuitry to receive said indications therefrom and responsive thereto coupling task status words associated with said process status word from said task status word memory;
• a control pipeline for receiving said process status words and said task status words from said process status word memory and said status word memory and processing the same through said control pipeline, said control pipeline responsive to said received process status words and said task status words providing sequential instruction outputs;
• memory means for storing data to be processed;
• a plurality of function units connected with said memory means;
• and
• coupling means for coupling said instruction outputs from said control pipeline to said memory means and said plurality of function units for controlling withdrawal of data from said memory means and causing the same to be processed by said function units concurrently with processing of said tasks.

An instruction processing device, comprising:

• at least one first-in, first-out buffer adapted to receive process data word pointers for storage therein;
• snapshot circuitry connected with said first-in, first-out buffer to sequentially draw said pointers therefrom and provide indications thereof;
• a process status word memory connected with said snapshot circuitry to receive said pointers therefrom and responsive thereto coupling process status words from said process status memory;
• a control pipeline receiving said process status words from said process status word memory and processing the same through said control pipeline, said control pipeline responsive to said received process status words providing sequential instruction outputs;
• memory means for storing data to be processed;
• at least one function unit connected with said memory means;
• and
• coupling means for coupling said instruction outputs from said control pipeline to said memory means and said function unit for controlling withdrawal of data from said memory means and causing the same to be processed by said function unit.

A concurrent task and instruction processing device, comprising:

• a plurality of task first-in, first-oout buffers each of which is adapted to receive process status word pointers for storage therein;
• snapshot control circuitry connected with said plurality of first-in, first-out buffers for causing a snapshot to be made of the next pointer to be withdrawn from each of said task first-in, first-out buffers having pointers therein;
• pointer selection means connected with said plurality of task first-in, first-out buffers and said snapshot control circuitry for sequentially selecting each pointer in said task snapshot and coupling the same from said buffers;
• a process status word memory connected with said pointer selection means for providing process status word outputs therefrom is response to receipt of a said pointer from said pointer selection means;
• a task status word memory connected with said snapshot control circuitry for providing a task status word output associated with said process status word output coupled from said process status word memory;
• a memory address calculator connected with said process status word memory and said task status word memory to receive said outputs therefrom;
• an address calculator connected with said task status word memory;
• a decoder providing an output;
• a program memory connected with said memory address calculator and providing an output to said address calculator and said decoder;
• data memory means including a register memory and a constant memory connected with said program memory;
• and
• function units connected with said data memory means and said decoder for executing instruction with respect to data withdrawn from said memory means.

A process for concurrently processing task and instructions, said process comprising:

• providing task components to be processed;
• providing indicators of said task components, said indicators of said task components being status word pointers;
• storing said pointers in buffers;
• sequentially processing said task components including withdrawing said indicators from said storage and utilizing said withdrawn indicators to concurrently generate multiple instructions for data processing by passing said components through a control pipeline to generate said multiple instructions;
• providing at least one function unit for acting upon data to be processed;
• and
• executing said instructions concurrently with processing of said task components to thereby cause said function unit to act upon said data to process the same.

A method for generating and processing of instructions, said method comprising:

• providing process components;
• providing indicators of said process components, said indicators being status word pointers;
• providing process component indicator storage including storing said pointers in at least one buffer;
• sequentially processing said process components to generate multiple instructions for data processing by sequentially withdrawing said indicators from said storage and utilizing said withdrawn indicators to cause said sequential processing of said process components by passing said components through a control pipeline to generate said multiple instructions;
• providing at least one function unit for acting upon data to be processed;
• and
• executing said instructions concurrently with processing of said process components to thereby cause said function unit to act upon said data to process the same.

A process for concurrently processing task and instructions, said process comprising:

• storing process status word pointers in buffers;
• storing process status words and task status words in word memories;
• withdrawing said pointers in sequence from said buffers and utilizing the same to cause withdrawal of process status words and an associated task status word from said word memories;
• passing said process status words and associated task status words through a control pipeline to generate multiple instructions;
• storing data in a data storage memory;
• providing a plurality of function units to act upon data;
• and
• utilizing said instructions to cause data to be withdrawn from said data storage memory and acted upon by said function unit concurrently with processing of said process status words and associated task status word through said control pipeline.