Ultra high speed complementary MOS device

A semiconductor device comprising:

• a body of semiconductor material having a major surface, said body being predominantly of one conductivity type and including first and second spaced-apart well regions of the opposite conductivity type extending into the body from said surface,
• a first metal-insulator-semiconductor field effect transistor formed at a location on said body surface lying within said first well region, said location including surface portions of relatively higher and lower elevation joined by a slope,
• said first transistor including a first region of said one conductivity type extending into said body at said higher surface portion and a second region of the same conductivity extending into said body at said lower surface portion, said first and second regions constituting source and drain regions for the transistor, a thin, implanted layer of said opposite conductivity type having an edge that terminates along said slope intermediate said first and second regions and constitutes a channel region for the transistor, said layer being more highly doped than said first well region, an insulating layer disposed over a portion of the body surface including the region thereof extending between said first and second regions, first and second electrodes making electrical contact with said source and drain regions, respectively, and a gate electrode disposed on said insulating layer overlying at least the portion of said slope that includes said channel region,
• a second, complementary metal-insulator-semiconductor field effect transistor of the double diffusion self-aligned type formed at an adjacent location on said body that includes said second well region, the surface at said adjacent location being substantially planar,
• said second transistor including a spaced-apart pair of regions of said opposite conductivity type extending into said body at opposite sides of said second well region and constituting source and drain regions for said second transistor, said source and drain regions being more highly doped than said well region, a narrow region of said one conductivity type surrounding said source region and separating it from said second well region, said narrow region being formed by a double diffusion technique and constituting a channel region for said second transistor, the region of said well extending between said channel region and said drain region constituting a drift region for said second transistor, an insulating layer disposed on said body surface overlying said channel and drift regions, third and fourth electrodes making electrical contact with said source and drain regions, respectively, and a gate electrode disposed on said insulating layer overlying said channel region.