A method of fabricating a very large scale integrated circuit chip comprising at least one silicon gate protected drain-source nonvolatile memory element having a channel of a first conductivity and a two layer silicon dioxide/silicon nitride gate insulator;
- said chip further comprising at least one insulated gate transistor having single layer silicon dioxide gate insulator;
- said method comprising the steps of:
- (a) providing a silicon wafer including an epitaxial layer of silicon having a second conductivity opposite from said first conductivity;
- (b) selectively doping a plurality of regions of the epitaxial layer with dopant ions to change the conductivity of the plurality of regions to the second conductivity, the plurality of regions including at least one first region and one second region respectively corresponding to the source and drain regions of each of at least one protected drain-source non-volatile memory element and at least one third region and one fourth region respectively corresponding to the source and drain regions of each of at least one insulated gate transistor;
- (c) selectively applying a first thick layer of silicon dioxide on the surface of the epitaxial layer in a region corresponding to the fixed threshold gate region of each of at least one protected drain-source nonvolatile memory elements;
- (d) selectively applying a second thin layer of silicon dioxide on the surface of the epitaxial layer in a region corresponding to the variable threshold gate region of each of at least one protected drain-source nonvolatile memory elements;
- (e) selectively applying a layer of silicon nitride on the surface of the first and second silicon dioxide layers;
- (f) selectively applying a third thick layer of silicon dioxide on the surface of the epitaxial layer in a region corresponding to the gate region of each of at least one insulated gate transistor;
- (g) selectively applying a layer of one of either polycrystalline silicon or metal on at least the surface of the third silicon dioxide layer and the silicon nitride layer;
- (h) selectively applying an insulated passivation layer on the surface of the very large scale integrated circuit chip, the passivation layer including windows therein, whereby regions of the chip to be electrically connected to are left exposed;
- (i) selectively applying a conductive layer to the surface of the passivation layer and the exposed regions of the chip, wherein electrical connections to the chip are formed.