Analog to digital converter utilizing a quantizer network

An analog to digital converter for quantizing an analog input signal into 2.sup.N quantization levels of increasing significance each level separated by a quantization differential and for converting each level into an N bit output code comprising:

• a resistive reference network for providing said 2.sup.N quantization levels;
• a resistive signal network coupled to receive said analog input signal;
• 2.sup.N differential amplifier means each coupled to said resistive reference network and said resistive signal network for comparing said analog input signal with said 2.sup.N levels to determine which are exceeded, said 2.sup.N differential amplifier means forming first and second sections, said differential amplifier means representing for each section a range of order of significance varying between most and least significance;
• 2.sup.N-1 -1 latching means each coupled to two of said differential amplifier means, one in each of said first and second sections and of the same relative order of significance in both sections;
• a position latching means and a most significant latching means respectively coupled to the differential amplifier means of most significance in said first and second sections, each of said 2.sup.N-1 -1 latching means and said most significant latching means providing output signals representing a cyclic bit position of different significance of a cyclic code having a count of N sequential code numbers, said position latching means representing the count of said cyclic code exceeding said N sequential code numbers, said cyclic code changing the state of only one cyclic bit position between sequential cyclic code numbers, and
• encoding means responsive to said latching means to provide said N bit output code and a position bit, whereby each of said 2.sup.N-1 -1 latching means changes states in response to differential amplifier means responding to quantization levels that are separated by half of the 2.sup.N quantization levels.

An analog to digital converter for quantizing analog input signals into 2.sup.N levels and converting each level into a N-bit output code comprising:

• a resistive reference network being divided into first and second sections;
• a resistive signal network responsive to said analog input signals and being divided into first and second sections;
• 2.sup.N differential amplifier means representing 2.sup.N quantization levels and divided into first and second groups respectively coupled to said first and second sections, the differential amplifier means of each group having a group order of significance;
• 2.sup.N-1 -1 latching means each coupled to a pair of said differential amplifier means with each pair being a differential amplifier means in both said first and second groups and of the corresponding group order of significance;
• a position bit latching means and a most significant bit latching means respectively coupled to the differential amplifier means of the most group order of significance in said first and second groups;
• said 2.sup.N-1 -1 and said most significant bit latching means developing binary output signals representative of a cyclic code having a bit position for each latching means and having a count of 2.sup.N states each count representing a sequential code number, said position bit latching means developing a binary output signal representative of the count exceeding said 2.sup.N states, said 2.sup.N-1 -1 latching means changing to opposite states in response to the analog input signal changing level an amount equal to half of the 2.sup.N-1 quantization levels;
• reset means coupled to said 2.sup.N-1 -1, said most significant bit latching means and said position bit latching means for periodically resetting said latching means;
• and
• encoding means responsive to said 2.sup.N-1 -1 and said most significant bit latching means for encoding each of said 2.sup.N states of said cyclic code into a unique number of said N bit output code.

An analog to digital converter for quantizing analog input signals and providing a binary output code comprising:

• a reference divider network of a series of resistors of value R and having reference taps therealong of increasing significance for providing threshold voltages with the voltage between adjacent reference taps being the quantization differential, said reference divider network having first and second sections each including a group of reference tap points,
• a signal divider network of a series of resistors of value R and having signal taps therealong of increasing significance, said signal divider network having first and second sections each including a group of signal tap points,
• 2.sup.N differential amplifiers forming first and second groups thereof, the differential amplifiers of each group having a similar relative order of significance, each differential amplifier having a first and second input terminal respectively coupled to a reference and a signal tap point for corresponding first and second sections of said reference and signal divider networks and of the same relative order of significance for providing a quantized signal, said differential amplifiers each drawing equal bias currents at said first and second input terminals,
• 2.sup.N-1 -1 latching means coupled to 2.sup.N-1 -1 differential amplifiers of least significance in said first and second groups, each coupled to a differential amplifier in both said first and second groups of the same relative order of significance, a position bit latching means and a most significant bit latching means respectively coupled to the differential amplifier of the most order of significance in the first and second groups said 2.sup.N-1 -1 and said most significant bit latching means providing output signals representative of a cyclic code of 2.sup.N sequential code numbers with each one of said 2.sup.N-1 -1 and said most significant bit latching means representing the cyclic bit position of a different significance of said cyclic code, said cyclic code changing the binary state of only one bit position between adjacent sequential code numbers, said bit positions each having a first binary state for one half of said 2.sup.N sequential code numbers and a second binary state for the remainder of the code numbers, each of said 2.sup.N- 1 -1 latching means changing state only twice for said cyclic code at sequential code numbers separated by one half of said 2.sup.N code numbers, and
• encoding means responsive to said latching means to provide a binary output code,
• whereby each of said 2.sup.N-1 -1 latching means responds to a differential level that is a function of the differential quantization levels included between the tap points of corresponding significance of the first and second sections of said reference and signal divider networks.

An analog to digital converter for quantizing analog input signals into 2.sup.N levels and converting each level into an N-bit code comprising:

• a resistive reference network having a series of directly connected resistors of value R, each reference network having reference tap points between the directly connected resistors and providing bias currents;
• a resistive signal network having a series of directly connected resistors of value R and being responsive to said analog input signals, each signal network having signal tap points between the directly connected resistors and bias currents;
• 2.sup.N differential amplifier means representing 2.sup.N quantization levels and being divided into first and second groups, each differential amplifier means having first and second input terminals, each differential amplifier means of said first and second groups respectively coupled to reference tap points and signal tap points of said respective resistive reference network and said resistive signal network, the differential amplifier means of each group having a group order of significance, each of said differential amplifier means cancelling error voltages developed by bias currents in said reference network and said signal network;
• 2.sup.N-1 -1 latching means each coupled to a different differential amplifier means in both said first and second groups and of the corresponding group order of significance, the coupling being to all of said differential amplifier means in each group except the two differential amplifier means of most group order of significance;
• a position bit latching means and a most significant bit latching means respectively coupled to the differential amplifier means of most group significance in said first and second groups, said 2.sup.N-1 -1 latching means and said most significant bit latching means developing binary output signals representative of a cyclic code having a bit position of different significance for each latching means and having 2.sup.N count states each represented by a sequential code number and in which only one bit changes binary state at a time between sequential code numbers, said position bit latching means representing that the count state exceeds said 2.sup.N count states, and
• encoding means responsive to said 2.sup.N-1 -1 latching means and said most significant bit latching means for encoding each of said code numbers of said cyclic code into a unique number of said N bit code.

An analog encoder for providing quantized voltages in an analog to digital converter responsive to a source of analog input signals comprising:

• a plurality of sources of reference potential,
• a reference network coupled to said plurality of sources of reference potential and having a plurality of resistors directly connected in series each having an equal value R with quantized reference tap points therebetween, with each reference tap point having a relative order of significance,
• a signal network coupled to said source of analog input signals and having a plurality of resistors of equal value R directly connected in series with signal tap points therebetween, with each signal tap point having a relative order of significance,
• a plurality of differential amplifiers, each having first and second input terminals respectively coupled to tap points of corresponding order of significance of said reference network and said signal network and passing equal bias currents through said first and second inputs of said differential amplifier, each of said differential amplifiers responding to the difference between the voltage at the reference tap point and the voltage at the signal tap point to provide the quantized voltage of a different order of significance, and
• each of said reference tap points having an error voltage provided by bias currents in said reference network and each of said signal tap points having an error voltage provided by bias currents in said signal network that is equal to the error voltage of the corresponding reference tap point,
• whereby the quantized voltages at the outputs of said differential amplifiers are substantially unaffected by the error voltages caused by the bias currents in said signal network and said reference network.

An analog encoder for providing quantized voltages in an analog to digital converter responsive to a source of analog input signals comprising:

• a plurality of sources of reference potential;
• a reference network coupled to said plurality of sources of reference potential and having a plurality of resistors each of value R directly connected in series, with quantized reference tap points therebetween, each tap point having a relative order of significance;
• a signal network coupled to said source of analog input signals and having a plurality of resistors, each of value R directly connected in series, with signal tap points therebetween, each tap point having a relative order of significance;
• a plurality of differential amplifiers, each having first and second inputs respectively coupled to reference tap points and signal tap points of corresponding order of significance and passing equal bias currents through said first and second inputs of said differential amplifier, each of said differential amplifiers responding to the difference between the voltage at the reference tap point and the voltage at the signal tap point for providing said quantized output voltages, and
• the bias currents in said reference network and said signal network providing an error voltage at each of said reference and signal tap points, said tap points of the same relative order of significance having equal error voltages,
• whereby the quantized voltages at the outputs of said plurality of differential amplifiers are substantially unaffected by the error voltages caused by the bias currents in said signal network and said reference network.

An analog encoder for providing quantized output voltages in response to a source of analog input signals comprising:

• a plurality of differential amplifiers each having first and second input terminals and providing substantially equal impedance characteristics to current passing through said terminals;
• a resistive reference network having a plurality of resistors directly connected in series, each of value R and having a plurality of quantized reference tap points therealong, each tap point being between two directly connected resistors, each tap point having a relative order of significance and each coupled to the first input terminal of a different differential amplifier and providing a bias current through said first input terminal;
• and
• a resistive signal network coupled to said source of analog input signals, said resistive signal network having a plurality of resistors directly connected in series, each of value R, and having a plurality of quantized signal tap points therealong, each tap point being between two directly connected resistors, each tap point having a relative order of significance and each coupled to the second input terminal of a differential amplifier being coupled to the tap point of said reference network of corresponding order of significance, each tap point providing a bias current, during the presence and the absence of an analog input signal, through the second input terminal equal to the bias current through the first input terminal of the corresponding differential amplifier;
• said bias currents for each differential amplifier developing substantially equal error voltages at the first and second input terminals of that differential amplifier,
• whereby the quantized output voltages from said differential amplifiers are substantially independent of the error voltages caused by the bias currents in said resistive reference network and said resistive signal network.