Zero reference and offset compensation circuit

Abstract

A zero reference and offset compensation circuit for an operational amplifier operating in the inverting mode in order to correct for both current and voltage offset errors. The zero reference and offset compensation circuit includes comparators for comparing the zero condition output of the operational amplifier with representations of lower and upper boundary signal levels, a pair of digital-to-analog converters having their respective analog outputs connected through appropriate scaling networks to the inverting input terminal and to the non-inverting input terminal of the operational amplifier, a microprocessor connected to the output of the comparators for providing an input to the associated digital-to-analog convertor so it produces an incremented digital signal whenever the comparators indicate the zero condition signal output exceeds either boundary signal level, the incremented digital signal being incremented in a direction to drive the associated digital-to-analog converter in a direction to bring said zero condition signal within the boundary which has been exceeded. The microprocessor has a current range selection capability so that the digital-to-analog converter connected to the inverting terminal is incremented for nanoampere range signal currents and the digital-to-analog converter associated with the non-inverting terminal is incremented for signal currents in the microampere range and above.

Dependencies are inferred from the claim text.