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US 4,229,474 AGranted
Breakage resistant V-grooved <100> silicon substrates
AssigneeTRW Inc.
InventorAlan L. Harrington
Life of this patent
Estimating the term…
Abstract
Flat and parallel depositions of low pressure chemical vapor deposited (LPCVD) polycrystalline intrinsic silicon are formed on both sides of a wafer of P-I-N <100> substrate of silicon to support the wafer during subsequent polish removal from the top surface. This structurally reinforces the crystal wafer and helps prevent warpage and cracking during subsequent handling.
Claims4
A crystalline semiconductive wafer comprising a plurality of V-grooves which are aligned to enable the separation of semiconductive crystals by breaking of the wafer along the V-grooves;
- a thin polycrystalline intrinsic silicon layer, of approximately 7 to 10 microns in thickness, applied onto the top and bottom sides of the substate;
- and
- a thick polycrystalline intrinsic silicon layer, sufficient to fill the grooves, applied over the thin polycrystalline intrinsic silicon layer on the top, the grooved side, of the substrate.
Dependencies are inferred from the claim text.