Apparatus for controlling a coin sorting machine

A coin sorting machine of the type having a sorting means in a coin passageway for discriminating between true and false inserted coins and for providing corresponding true and false coin sorting signals, and a controllable segregating member for segregating a coin in a true coin direction or a false coin direction in response to said true and false sorting signals, respectively, the improvement comprising:

• first coin detector means upstream of said segregating member for providing a first coin detection signal indicating the passage of a coin;
• second coin detector means upstream of said segregating member and downstream of said first detector for providing a second coin detection signal indicative of the passage of a coin;
• and
• logic circuit means for receiving said first and second detection signals and controlling said segregating member to segregate coins in a false coin direction when two first detection signals are received in succession without an intervening second coin detection signal;
• said logic circuit means comprising:
• first flip-flop means switched to a set condition by said first coin detection signal to provide a first set signal, and switched to a reset condition by said second coin detection signal to provide a first reset signal;
• first AND circuit means responsive to the simultaneous appearance of said first set signal and a following first coin detection signal to produce a first AND signal;
• second flip-flop means switched to a set condition by said first AND signal to produce a second set signal, and switched to a reset condition by said second coin detection signal to produce a second reset signal;
• third flip-flop means switched to a set condition by a true coin sorting signal to produce a third set signal, and switched to a reset condition by said first reset signal to produce a third reset signal;
• second AND circuit means responsive to the simultaneous occurrence of said second reset signal, said third set signal and said second coin detection signal to produce a second AND signal;
• fourth flip-flop means switched to a set condition by said second AND signal to produce a control signal indicative of the detection of an inserted true coin spaced at least a predetermined minimum time from a following inserted coin, said segregating member being controlled by said control signal to segregate the true coin in said true coin direction;
• third AND circuit means responsive to the simultaneous occurrence of said second set signal and said second coin detecting signal to produce a third AND signal;
• said fourth flip-flop means being switched to a reset condition by said third AND signal thereby to inhibit the production of said control signal so that said true coin is segregated in said false coin direction when the time between two successively inserted coins is less than said predetermined time;
• and
• fourth AND circuit means responsive to said third reset signal and said second coin detection signal to provide a fourth AND signal;
• said fourth flip-flop means being switched to the reset condition by said fourth AND signal thereby also to inhibit the production of said control signal so that said segregating member segregates a false coin in said false coin direction.