Electrically reprogrammable non volatile memory

An electrically reprogrammable non-volatile memory device comprising an integrated circuit including complementary MOS transistors provided with a polycrystalline silicon floating gate electrode, in a common n.sup.- -type substrate which forms the grounded electrode, wherein said circuit is composed of three parts:

• the first part being utilized to perform writing of information and addressing;
• the second part being utilized to perform erasure;
• and the third part being utilized to perform read-out of the information;
• said floating gate electode forming a common electrode to said three parts of the device;
• said first part comprising a p-channel writing transistor, having its drain, which provides a p.sup.+ -n junction for injection of electrons, connected, on the hand, to the drain of a p-channel control transistor the source of which is grounded, and, on the other hand, to a resistance element which is connected to a terminal delivering a high negative voltage during the writing operation;
• said second part of the circuit comprising a second gate electrode which is capacitively coupled to said floating gate electrode in such a manner that the electric field between both electrodes is lower than the electric field across the gate oxide layer of the said transistors, and said second gate electrode being connected to a terminal delivering a high negative voltage during the erasure operation;
• and
• said third part of the circuit consisting of a p-channel read-out transistor, the source of which is grounded, its gate forming a portion of the floating gate electrode and its drain being connected to a read-out terminal and to a terminal of a loading element having its other terminal connected to a negative supply voltage.