Microprocessor having multiply/divide circuitry
AssigneeMotorola, Inc.
InventorGeorge P. Chamberlin
Life of this patent
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Abstract
A microprocessor having the capability of performing either a multiply or divide operation from a single instruction for each operation is provided. Much of the standard circuitry of a microprocessor is used along with a multiply/divide cycle counter, logic circuitry, and a shift network separate from the arithmetic logic unit. The microprocessor has the capability of performing unsigned integer multiplication and division. A shift and add algorithm is used for multiplication while for division a non-restoring divide algorithm is used.
Claims8
A microprocessor having circuitry for multiplying or dividing, comprising:
- an arithmetic and logic unit;
- a first register for holding a multiplier and for holding a least significant portion of a binary number to be divided and for containing a quotient upon completion of a division;
- a second register for holding a most significant portion of a product obtained from a multiplication routine and for holding the most significant portion of the binary number to be divided and for storing a remainder obtained from a divide routine, the second register being coupled to the arithmetic and logic unit;
- a shift network coupled to the arithmetic and logic unit and coupled to the first and second registers for shifting data outputted by the arithmetic and logic unit;
- logic circuitry coupled to the arithmetic and logic unit and to the first register for controlling the multiplying and dividing;
- and a counter coupled to the logic circuitry for counting microprocessor clock cycles elapsed during multiplication and during division.
A microprocessor with multiply or divide capability and having storage means for storing the multiplicand for a multiplication routine and for storing the divisor for a division routine, an arithmetic and logic unit, and a data bus for transferring data from the storage means during multiplication and division, comprising:
- first means coupled to the arithmetic and logic unit for shifting data from the arithmetic and logic unit, the first means providing an output;
- a first register coupled to the arithmetic and logic unit and to the first means for receiving the output of the first means;
- a second register for storing a plurality of bits and being coupled to the first means and having a least significant bit;
- second means for providing logic control functions during multiply and during divide and being coupled to the arithmetic and logic unit and to the second register;
- and a cycle counter to count cycles of a multiply and of a divide and being coupled to the second means to provide an indication of the last cycle of a multiply and of a divide.
Dependencies are inferred from the claim text.