Virtual addressing for I/O adapters

In a virtual memory computer system having a central processing unit, main memory and I/O adapters connected to the main memory by a channel, wherein said main memory has a plurality of addressable storage locations and a group of storage locations form a memory page having memory address boundaries, wherein both the CPU and the I/O adapters use virtual addressing and wherein the channel has a priority mechanism for granting use of the channel to the highest priority I/O adapter requesting use of the channel, the improvement comprising:

• an I/O address register for storing a memory address for addressing memory;
• register means for storing memory addresses, where the register means is accessible by the channel and the CPU;
• incrementing means for incrementing the memory address in the I/O address register;
• detecting means for detecting when the incrementing means increments the memory address in the I/O address register to a value for addressing a memory location across a memory page boundary, said incremented memory address becoming invalid upon reaching the value for addressing a memory location across a memory page boundary;
• means for translating an incremented memory address in said I/O address register which crosses a page boundary into a valid main memory address and for providing a translation completion signal to the channel upon completion of the address translation;
• and
• disconnection means in the channel for disconnecting an I/O adapter from the channel when the I/O adapter requests use of the channel and the I/O address register after the detecting means has detected that a memory address in the I/O address register has crossed a page boundary, said disconnection means holding said I/O adapter disconnected when said I/O adapter requests use of the channel and the I/O address register until the channel receives the translation completion signal indicating completion of address translation, said disconnection means otherwise permitting the I/O adapter to request and use the channel via said register means and provided use of the I/O address register is not requested.