Interface unit for data exchange between a central processor and a peripheral unit in TDM telecommunication system

In a TDM telecommunication system wherein a central processor dialogues with a plurality of peripheral units each having a multiplicity of loads activable in time slots individually assigned thereto in a recurrent scanning cycle,

• the combination therewith of an interface unit interposed between said processor and an associated peripheral unit, said interface unit comprising:
• a receiving section with first input means connected to said processor and first output means connected to the associated peripheral unit;
• a transmitting section with second input means connected to the associated peripheral unit and second output means connected to said processor;
• first register means in said receiving section connected to said first input means for the temporary storage of incoming messages from said processor, said incoming messages including signalization messages and supervisory messages distinguished by different digital labels;
• second register means in said transmitting section connected to said second input means for the temporary storage of return messages from the associated peripheral unit;
• memory means in said receiving section having a multiplicity of cells connected to said first output means, said cells being respectively allocated to said loads and identified by address codes of said signalization messages corresponding to the time slots assigned thereto;
• timer-operated first control means in said receiving section responsive to a signal from said first register means for directing the writing of an operative code of an incoming message, destined for a load of the associated peripheral unit identified by an accompanying address code, in the allocated cell of said memory means during one part of a time slot and for commanding the readout to said first output means, during another part of a time slot, of the contents of the cell allocated to the load which is activable in the immediately following time slot, said first control means including first instruction means for routing said supervisory messages from said receiving section to said transmitting section;
• and
• second control means in said transmitting section responsive to a signal from said second register means for routing return messages from the associated peripheral unit to said second output means, said second control means including second instruction means for retransmitting responses to said supervisory messages from said interface unit to said processor by way of said second output means.