Multibus processor for increasing execution speed using a pipeline effect

A computing apparatus for carrying out a plurality of elemental machine operations during one instruction cycle of the apparatus comprising:

• a plurality of elementary function modules,
• at least three buses, each bus comprising a plurality of individual lines, said individual lines being organized at least into
• a group of source address lines,
• a group of destination address lines, and
• a group of data carrying lines,
• a first one of said function modules being connected at least to the data and one other group of lines of a first one of said buses, a second one of said modules each being connected at least to said data and one other group of lines of a second one of said buses, a third one of said modules being connected at least to the data and one other group of lines of a third one of said buses, and a fourth one of said modules being connected at least to the data and one other group of lines of each of the first, second, and third buses,
• each other of said plurality of modules being connected at least to said data and one other group of lines of a respective bus whereby each source and destination group of each of said plurality of buses is connected to at least one of said plurality of function modules, and each data group of each of said plurality of buses is connected to at least two of said plurality of function modules, and
• a control means, said control means being connected to all of said bus lines for directing the operation of said function modules and having the capability of effectively configuring the function modules by placing addresses on selected ones of said source and destination address lines of said at least three buses for carrying out said at least four elemental operations on a parallel basis within a said one instruction cycle, each elemental operation normally individually requiring up to the duration of one instruction cycle to complete.

A computing apparatus for carrying out a plurality of elemental machine operations during one instruction cycle of the apparatus comprising

• a plurality of elementary function modules,
• a first, a second, and a third bus, each bus comprising a plurality of individual lines, said individual lines being organized into
• a group of source address lines,
• a group of destination address lines,
• a group of data carrying lines, and
• a group comprising at least one bus enable line,
• a first one of said function modules being connected at least to the data, the bus enable, and one of the source and destination group of lines of said first bus, a second one of said function modules each being connected at least to the data, the bus enable, and one of the source and destination group of lines of said second bus, a third one of said function modules being connected at least to the data, the bus enable, and one of the source and destination group of lines of said third bus, and a fourth one of said modules being connected at least to the data, the bus enable, and one of said source and destination group of lines of each of said first, second, and third buses,
• each other of said plurality of modules being connected at least to the data, the bus enable, and one of said destination and source group of lines of a respective bus whereby each bus enable, source, and destination group of each of said three buses is connected to at least one of said plurality of function modules,
• each function module comprising
• a function circuit for performing an elemental operation,
• an input storage register connected to said function circuit for loading data from a bus and
• an output means for making data from said function circuit available to a bus,
• a control means, said control means being connected to all of said bus lines for directing the operation of the function modules and having the capability of effectively configuring the function modules by placing addresses on selected ones of said source and destination address lines of said three buses for carrying out said plurality of elemental operations on a parallel basis within a said one instruction cycle, each elemental operation normally individually requiring up to the duration of one instruction cycle to complete,
• the control means comprising;
• a master clock means for generating a timing signal for marking the beginning of each instruction cycle,
• a program control unit responsive to the timing signal for fetching successive instructions from a program memory,
• means responsive to the program control unit for providing source and destination addresses to said buses, and
• means responsive to the program control unit for selectively enabling the bus enable lines.