Analog video convolver for real time two-dimensional image processing

A real time two-dimensional analog video convolver for modifying picture element (pixel) signals in a system including a video monitor for displaying a picture composed of successive horizontal lines of pixels, said monitor having composite video signal input means, said system further including display controller means for storing pixel signals representative of a picture to be displayed and operative to convert said pixel signals to analog video signals for successive horizontal lines, said controller being operative to provide the composite video waveform signals including synchronizing signals for controlling the monitor and to provide pixel clock pulses to enable reading out the stored pixel signals in phase with their display by the monitor, said controller having output means for said composite video signal;

• said convolver comprising:
• a series of shift register means each having a predetermined number of stages and each having input and output means, the input means of the first register in the series being for coupling to the output means of said display controller, the output means of each register being coupled to the input means of said next register in the series,
• means synchronized by said clock pulses for supplying sample clock pulses and shift clock pulses to said shift register means, said register means responding to said sample clock pulses by taking a series of successive samples of the voltage of said video signal waveform for a horizontal line and responding to said shift clock pulses by transporting said samples through the stages of said register,
• said series of samples from the first register being clocked repeatedly to the next register to enable the first register to obtain the next series of samples in phase with the samples in the next register, the series of samples in each said next register thereby being increasing delayed with respect to a preceding register for the time of a video signal series and the samples in said first register being delayed for the time of one video signal series relative to the next video signal waveform which will occur in real time,
• a plurality of delay line means each of which is comprised of delay elements and each having input and output means, the input means of said first delay line means being coupled to the output means of said display controller and the input means of others of said plurality of delay line means being coupled to the output means of said registers, respectively,
• the number of stages in each of said shift registers exceeding by the same amount the number of pixels that are required to fill a horizontal line across the display screen of said video monitor, and including
• means operative for an interval after the pixel signals constituting the useful part of a video signal waveform for a horizontal line are outputted from said registers and before occurrence of the next horizontal sync pulse to increase the frequency of said shift clock pulses and sample clock pulses so that synchronism of sampling and the horizontal sync pulses will be maintained,
• plural sample and hold circuit means interposed, respectively, between said output means of the registers and the input means of said delay line means,
• means for gating said sample and hold circuits to transfer sample pixel signals from the respective output means of said registers to the delay line means to which they are coupled only between pixel clock and analog shift pulses,
• said delay line means each being operative to delay incoming pixel signals for periods of one or more pixels so that there will appear simultaneously at respective delay line output means delayed pixel signals from each horizontal line, said delayed pixel signals being maintained in a predetermined time relationship with each other,
• means for summing the majority of pixel signals appearing at any instant in said delay line output means, p1 means for optionally varying the magnitudes of said summed signals either negatively or positively,
• means for summing said summed signals with a selected one of the pixel signals from one of the delay elements to modify said one signal, and
• means for coupling the modified signal to said video signal input of the monitor.

A real time two-dimensional analog video convolver for modifying picture element (pixel) signals in a system including a video monitor for displaying a picture composed of successive horizontal lines of pixels, said monitor having composite video signal input means, said system further including display controller means for storing pixel signals representative of a picture to be displayed and operative to convert said pixel signals to analog video signals for successive horizontal lines, said controller being operative to provide the composite video waveform signals including synchronizing signals for controlling the monitor and to provide pixel clock pulses to enable reading out the stored pixel signals in phase with their display by the monitor, said controller having output means for said composite video signal;

• said convolver comprising:
• a series of shift register means each having a predetermined number of stages and each having input and output means, the input means of the first register in the series being for coupling to the output means of said display controller, the output means of each register being coupled to the input means of said next register in the sereis,
• means synchronized by said clock pulses for supplying sample clock pulses and shift clock pulses to said shift register means, said register means responding to said sample clock pulses by taking a series of successive samples of the voltage of said video signal waveform for a horizontal line and responding to said shift clock pulses by transporting said samples through the stages of said register,
• said series of samples from the first register being clocked repeatedly to the next register to enable the first register to obtain the next series of samples in phase with the samples in the next register, the series of samples in each said next register thereby being increasing delayed with respect to a preceding register for the time of a video signal series and the samples in said first register being delayed for the time of one video signal series relative to the next video signal waveform which will occur in real time,
• the number of stages in each of said shift registers exceeding by the same amount the number of pixels that are required to fill a horizontal line across the display screen of said video monitor, and including
• means operative for an interval after the pixel signals constituting the useful part of a video signal waveform for a horizontal line are outputted from said registers and before occurrence of the next horizontal sync pulse to increase the frequency of said shift clock pulses and sample clock pulses so that synchronism of sampling and the horizontal sync pulses will be maintained,
• a plurality of delay line means each of which is comprised of delay elements and each having input and outlet means, the input means of said first delay line means being coupled to the output means of said display controller and the input means of others of said plurality of delay line means being coupled to the output means of said registers, respectively,
• said delay line means each being operative to delay incoming pixel signals for periods of one or more pixels so that there will appear simultaneously at respective delay line output means delayed pixel signals from each horizontal line, said delayed pixel signals being maintained in a predetermined time relationship with each other,
• means for summing the majority of pixel signals appearing at any instant in said delay line output means,
• means for optionally varying the magnitudes of said summed signals either negatively or positively,
• means for summing said summed signals with a selected one of the pixel signals from one of the delay elements to modify said one signal, and
• means for coupling the modified signal to said video signal input of the monitor.

A real time two-dimensional analog video convolver for modifying picture element (pixel) signals in a system including a video monitor for displaying a picture composed of successive horizontal lines of pixels, said monitor having composite video signal input means, said system further including display controller means for storing pixel signals representative of a picture to be displayed and operative to convert said pixel signals to analog video signals for successive horizontal lines, said controller being operative to provide the composite video waveform signals including synchronizing signals for controlling the monitor and to provide pixel clock pulses to enable reading out the stored pixel signals in phase with their display by the monitor, said controller having output means for said composite video signal;

• and convolver comprising:
• first and second shift register means each having a predetermined number of stages and each having input and output means, the input means of said first register being for coupling to the output means of said display controller, the output means of said first register being coupled to the input means of said second register,
• means synchronized by said clock pulses for supplying sample clock pulses and shift clock pulses to said shift register means, said register means responding to said sample clock pulses by taking a series of successive samples of the voltage of said video signal waveform for a horizontal line and responding to said shift clock pulses by transporting said samples through the stages of said register,
• said series of samples from the first register being clocked repeatedly to the second register to enable the first register to obtain the next series of samples in phase with the samples in the second register, the series of samples in said second register thereby being delayed for the time of two video signal series and the samples in said first register being delayed for the time of one video signal series relative to the next video signal waveform which will occur in real time,
• first, second and third delay line means each of which is comprised of delay elements and each having input and output means, the input means of said first delay line means being coupled to the output means of said display controller and the input means of said second and third delay line means being coupled to the output means of said first and second registers, respectively,
• the number of stages in each of said shift registers exceeding by the same amount the number of pixels that are required to fill a horizontal line across the display screen of said video monitor, and including
• means operative for an interval after the pixel signals constituting the useful part of a video signal waveform for a horizontal line are outputted from said registers and before occurrence of the next horizontal sync pulse to increase the frequency of said shift clock pulses and sample clock pulses so that synchronism of sampling and the horizontal sync pulses will be maintained,
• sample and hold circuit means interposed respectively between said output of the first register and the input to said second delay line means and between said output of the second register and said input to said third delay line means,
• means for gating said sample and hold circuits to transfer sample pixel signals from the respective output means of said registers to the delay line means to which they are coupled only between pixel clock and analog shift pulses,
• said delay line means each being operative to delay incoming pixel signals for periods of one, two and three pixels, so that there will appear simultaneously at respective delay line output means first, second and third pixel signals from each horizontal line,
• means for summing the first and third pixel signals appearing in said first delay line output means with the first and third pixel signals appearing in said third delay line output means, said sum being designated the corner signal,
• means for summing the second pixel signal appearing in said first delay line output means with the first and third pixel signals appearing in said second delay line output means and with the second signal appearing in said third delay line means, said sum being designated the cross signal,
• said second signal appearing in said second delay line output means being designated the center signal,
• means for optionally varying the magnitudes of said cross and corner signals either negatively or positively,
• means for summing said cross and corner signals with said center signals to modify said center signals, and
• means for coupling said modified center signals to said video signal input of the monitor.

A real time two-dimensional analog video convolver for modifying picture element (pixel) signals in a system including a video monitor for displaying a picture composed of successive horizontal lines of pixels, said monitor having composite video signal input means, said system further including display controller means for storing pixel signals representative of a picture to be displayed and operative to convert said pixel signals to analog video signals for successive horizontal lines, said controller being operative to provide the composite video waveform signals including synchronizing signals for controlling the monitor and to provide pixel clock pulses to enable reading out the stored pixel signals in phase with their display by the monitor, said controller having output means for said composite video signal;

• said convolver comprising:
• first and second shift register means of the charge coupled type each having a predetermined number of stages and each having input and output means, the input means of said first register being for coupling to the output means of said display controller, the output means of said first register being coupled to the input means of said second register,
• means synchronized by said clock pulses for supplying sample clock pulses and shift clock pulses to said shift register means, said register means responding to said sample clock pulses by taking a series of successive samples of the voltage of said video signal waveform for a horizontal line and responding to said shift clock pulses by transporting said samples through the stages of said register,
• said series of samples from the first register being clocked repeatedly to the second register to enable the first register to obtain the next series of samples in phase with the samples in the second register, the series of samples in said second register thereby being delayed for the time of two video signal series and the samples in said first register being delayed for the time of one video signal series relative to the next video signal waveform which will occur in real time,
• the number of stages in each of said shift registers exceeding by the same amount the number of pixels that are required to fill a horizontal line across the display screen of said video monitor, and including
• means operative for an interval after the pixel signals constituting the useful part of a video signal waveform for a horizontal line are outputted from said registers and before occurrence of the next horizontal sync pulse to increase the frequency of said shift clock pulses and sample clock pulses to that synchronism of sampling and the horizontal sync pulses will be maintained,
• first, second and third delay line means each of which is comprised of delay elements and each having input and output means, the input means of said first delay line means being coupled to the output means of said display controller and the input means of said second and third line means being coupled to the output means of said first and second registers, respectively,
• said delay line means each being operative to delay incoming pixel signals for periods of one, two and three pixels, so that there will appear simultaneously at respective delay line output means first, second and third pixel signals from each horizontal line,
• means for summing the first and third pixel signals appearing in said first delay line output means with the first and third pixel signals appearing in said third delay line output means, said sum being designated the corner signal,
• means for summing the second pixel signal appearing in said first delay line output means with the first and third pixel signals appearing in said second delay line output means and with the second signal appearing in said third delay line means, said sum being designated the cross signal,
• said second signal appearing in said second delay line output means being designated the center signal,
• means for optionally varying the magnitudes of said cross and corner signals either negatively or positively,
• means for summing said cross and corner signals with said center signals to modify said center signals, and
• means for coupling said modified center signals to said video signal input of the monitor.