Submicron channel length MOS inverter with depletion-mode load transistor

A monolithic metal-insulator-semiconductor inverter circuit structure of the combined enhancement/depletion-mode type, comprising:

• a body of semiconductor material predominantly of one conductivity type, said body having a major surface that includes a substantially planar field and an adjoining nonplanar field with surface portions of relatively higher and lower elevation joined by a slope,
• an enhancement-mode field effect device at least partially formed within said nonplanar surface field, said device including (a) a first, heavily doped region of the other conductivity type extending into said body at said higher surface portion, (b) a second, heavily doped region of said other conductivity type extending into said body at said lower surface portion, said first and second regions respectively constituting source and drain regions for said enhancement-mode device, (c) a thin layer of said one conductivity type formed by implantation within said body beneath said first impurity region and including an upturned margin that terminates at said slope and constitutes a channel region for said device, (d) a third, more lightly doped region of said other conductivity type extending along said body surface between said channel region and drain region and constituting a drift region for said device, (e) a first insulating layer disposed over a portion of the body surface in said nonplanar field, including the portion extending between said first and second regions, and (f) a first gate electrode disposed on said first insulating layer overlying said channel and drift regions, and
• a depletion-mode field effect device integrated with said enhancement-mode device, and including (a) a fourth, heavily doped region of said other conductivity type extending into said body within said planar field at a location spaced from said second region by (b) a fifth, more lightly doped region of said other conductivity type, said second and fourth and fifth regions respectively constituting source, drain and channel regions for the depletion mode device, (c) a second insulating layer disposed over a portion of the body surface in said planar field, including the portion extending between said second and fourth regions, and (d) a second gate electrode disposed on said insulating layer overlying said fifth region.