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US 4,228,423 AGranted
Offset correction apparatus for a successive approximation A/D converter
AssigneeThe United States of America as represented by the Secretary of the Air Force
InventorChristopher B. Schwerdt
Life of this patent
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Abstract
An offset correction apparatus for a successive approximation analog to digital converter which will correct the A/D converter-derived offset voltage as referred to the analog input to within .+-.1mV of a preset reference over a wide temperature range.
Claims6
A successive approximation analog-to-digital converter in combination with an offset correction generating means and offset correction control means wherein
- said converter includes a successive approximation register for providing a successive approximation digital signal upon receipt of an analog input signal, a digital-to-analog converter connected to the output of said successive approximation register, a comparator having an output for connection to the input of said register, a dual input amplifier connected between said digital-to-analog converter and an input to said comparator, said comparator also being connected to receive the input analog signal to be digitized by the analog-to-digital converter,
- said offset correction generating means being connected to receive an offset reference voltage and selectively connected to receive the output from said dual input amplifier to provide an offset correction output signal which is applied to the other input of said dual input amplifier, the output of which is an offset correction voltage;
- and
- said offset correction control means controls the selective connection of said offset correction generating means to said comparator, said correction control means including a logic gate connected between said comparator and said successive approximation register, said logic gate being operable upon receipt of a pretrigger signal to interrupt the normal analog-to-digital conversion and force said successive approximation register to have a predetermined state imposed thereon such that the correction voltage output from said dual input amplifier may be applied to said successive approximation register through said logic gate.
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Dependencies are inferred from the claim text.