Low voltage compound inverter buffer circuit
AssigneeNational Semiconductor Corporation
InventorRobert J. Widlar
Life of this patent
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Abstract
An integrated circuit gain block is obtained by cascading a common collector stage with a complementary common emitter stage. The current density of the common emitter transistor is made sufficiently greater than that of the common collector transistor so that the common emitter V.sub.BE lowest worst case value is higher than the common collector V.sub.BE highest worst case value. This makes the circuit manufacturable in integrated circuit form and permits the circuit to operate from a single power supply potential that can be as low as the series combination of one V.sub.BE added to one transistor collector to emitter saturation voltage. The circuit has a high current gain and is amenable to incorporation into current boosted class B amplifier output stages.
Claims6
A compoud buffer inverter for use in an integrated circuit that employs a single power supply connectible between first and second supply rails and that is particularly adapted for operation at low power supply voltages, said compound buffer inverter being operative to provide substantial current gain with a single signal polarity inversion and level shifting capability, said compound buffer inverter comprising:
- a first transistor having its emitter coupled to said first rail, its collector providing a current output terminal capable of assuming a potential between said first and second rails and a base;
- a second transistor complementary of said first transistor, said second transistor having a collector coupled to said first rail, an emitter coupled to said base of first transistor, and a base coupled to a circuit input terminal;
- current supply means coupled between said base of said first transistor and said second rail;
- means for operating said first transistor such that its emitter base potential is equal to or greater than the emitter base potential of said second transistor;
- and means for boosting the bias current to said first and second transistors with increasing load current.
A monolithic integrated circuit having opposite and negative rails connectible to a single source of operating potential, said circuit comprising:
- a first NPN transistor having its collector emitter circuit coupled to act a current sink between an output terminal and said negative rail and a base;
- a second PNP transistor having its emitter collector circuit coupled to act as a current sink between said base of said first transistor and said negative rail and a base;
- a current supply source coupled between said positive rail and said collector emitter circuit of said second transistor;
- means for coupling said base of said second transistor to an input terminal;
- means for operating said first transistor at a higher current density than said first transistor whereby said base of said second transistor operates at a potential close to and above said negative rail and there is substantial gain between said input and output terminals;
- a third NPN transistor having an emitter base circuit coupled in parallel with the emitter base circuit of said first transistor and a collector;
- a fourth PNP transistor having its collector and base coupled together and to said collector of said third transistor and its emitter coupled to said positive rail;
- and
- a fifth PNP transistor having its base coupled to said collector of said third transistor, its emitter coupled to said positive rail and its collector coupled to said base of said first transistor, whereby the base current drive to said first transistor is boosted as a function of its emitter-base voltage drive.
Dependencies are inferred from the claim text.