Integrator circuit with limiter

#Integrator circuits of the type described herein are for instance used for forming pulses. They enable rising and dropping portions of predetermined slopes to be generated, with a zone of constant voltage defined by the limitation arranged therebetween.

#There exist essentially two different ways of obtaining such limitation. In the case of the active limitation, a control circuit is activated to maintain the voltage at the capacitor constant, when the limit voltage has been reached. For this purpose, the amplification of the control circuit must be kept low to allow rapid transient of the control circuit. However, this means that the limiting voltage does not remain constant and that the difference between the start and the final value of the limitation is relatively high.

#In the case of the passive limitation, a clamping circuit with diodes is used which receives the constant current previously supplied to the capacitor after the clamping voltage has been reached. However, the particular current/voltage characteristic of the diodes results in a voltage discontinuity during the transition from the constant clamping voltage to the dropping slope (discharge of the capacitor), and as a result thereof the pulse shape becomes inaccurate. Although this voltage discontinuity can be avoided by passing the pulse through an additional limiter circuit which clips off the inaccurate portion of the pulse, such procedure offers the disadvantage that the contant-voltage time varies with any change of the slope of the rising and/or dropping portion. However, in many applications, it is desired that this contant-voltage section should remain uniformly long even if the slope should be varied.

#FIG. 1 shows a basic circuit diagram of an integrator in accordance with the invention;

#FIG. 2 shows the output voltage/time curve of the circuit shown in FIG. 1; and

#FIG. 3 shows a detailed circuit diagram of a preferred embodiment of the invention.

#FIG. 1 shows an integration capacitor C.sub.I that can be charged and/or discharged via current sources I.sub.R and I.sub.V. The capacitor voltage U.sub.c can be kept at an output terminal 11. Clamping circuits 13 and 13' prevent the capacitor voltage U.sub.c from rising above a predetermined value .+-.U.sub.cmax. Both the two current sources I.sub.R and I.sub.V and the clamping circuits 13 and 13' can be connected to the integration capacitor C.sub.I via switches S.sub.1, S.sub.2 and S.sub.3 or S.sub.3 '. The switches S.sub.1, S.sub.2, S.sub.3 and S.sub.3 ' can be actuated by means of a control circuit 15.

#Now, the switching sequence will be described in connection with FIG. 2, which shows the curve of the output voltage U.sub.c related to time. At the moment t.sub.o the switches S.sub.1 and S.sub.3 are closed, whereas the switches S.sub.2 and S.sub.3 ' remain open. This is the condition shown in FIG. 1. Then the capacitor C.sub.I is charged via the current source I.sub.R (FIG. 1) and as a result a sloping rise of the voltage U.sub.c is achieved until the clamping voltage U.sub.cmax is reached at the moment t.sub.1. Thereafter, this voltage is maintained until the moment t.sub.2.

#At the moment t.sub.2, the switches S.sub.1 and S.sub.3 are opened, whereas the switch S.sub.2 is closed, when the capacitor C is discharged via the current source I.sub.V, and as a result a sloping drop of the voltage U is achieved until the value zero is reached at the moment t.sub.3. About this moment, the switch S.sub.3 ' is closed. The capacitor C.sub.I continues to be negatively charged and the voltage U.sub.c continues to drop until the negative clamping voltage U.sub.cmax is reached at the moment t.sub.4. This voltage is then maintained until the moment t.sub.5.