US 4,227,251 AGranted

Clock pulse regenerator

AssigneesNippon Telegraph & Telephone Public Corporation, Nippon Electric Co., Ltd.

InventorsShigeru Kazama, Kouzou Kage

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Abstract

A clock pulse regenerator is constructed with digital circuits and may be built using large scale integration techniques. An oscillator produces first pulses at a repetition rate higher than that of the incoming digital data signal. A first counter counts the first pulses to produce the regenerated clock pulses. A gate pulse generator is responsive to both the incoming digital data signal and the regenerated clock pulses to generate a gate pulse having a pulse width proportional to a phase difference between the two signals. A third counter counts the number of leading and trailing edges of the incoming digital data signal. The pulse outputs of the second and third counters are supplied to a gate circuit. A fourth counter counts the pulses transmitted by the gate circuit to produce, after a predetermined count, a reset pulse for the first, second, third and fourth counters. The second, third and fourth counters therefore serve as a phase detector. The detection output resets the first counter which generates the clock pulse sequence with the received input.

Claims9

Dependent claims

A clock pulse regenerator for producing regenerated clock pulses in response to an incoming digital data signal, comprising:

an oscillator for producing first pulses at a repetition rate higher than that of said incoming digital data signal;
a first counter connected to said oscillator for counting said first pulses to produce said regenerated clock pulses therefrom;
gate signal generating means responsive to said incoming digital data signal and said regenerated clock pulses for generating a gate pulse having a pulse width proportional to a phase difference between the two received signals;
first gate means for selectively transmitting therethrough said first pulses under the control of said gate pulse;
a second counter for counting said first pulses from said first gate means and producing a second pulse every time the counted number reaches a fixed number;
a third counter for counting the number of leading and trailing edges of said incoming digital data signal and producing an output upon the counted number reaching said fixed number;
a second gate means for selecting said first and second pulses in accordance with said output of said third counter and producing a series of pulses in response to the selected first and second pulses;
and
a fourth counter for counting said series of pulses to produce a pulse upon counting a predetermined number of pulses whereby said pulse from said fourth counter resets said first, second, third and fourth counters.

6 more elements

Dependencies are inferred from the claim text.