Integrated circuit controller programmable with unidirectional-logic instructions representative of sequential wire nodes and circuit elements of a ladder diagram

In a programmable controller:

• main memory means for storing sets of instructions defining the configuration of a ladder diagram, each said set including the input wire number to a contact, the contact number, and the output wire number from the contact;
• means for performing an AND-logic function and storing the result comprising:
• means for reading said instructions in sequence;
• a plurality of status signal storage devices;
• a control clock;
• means responsive to reading of said input wire number instruction for setting said first storage device under said clock control indicative of the "on" state of said input wire number;
• means responsive to reading of said contact number instruction for setting said second storage device under said clock control indicative of the closed state of said contact provided said first storage device is set;
• means responsive to the setting of said second storage device for directly setting said third storage device indicative of the "on" state of said output wire number;
• an addressable wire number memory;
• and means controlled by said clock for storing the "on" state of said output wire number in said wire number memory at an address corresponding to said output wire number.

In an addressable programmable controller:

• main memory means for storing sets of instructions defining the configuration of a ladder diagram, each said set including the input wire number to an output device, a special code indicative of an output action, and the output device number;
• means for performing an AND-logic function and storing the result comprising:
• means for reading said instructions in sequence;
• a plurality of signal storage devices;
• a control clock;
• a wire number memory for storing the status of said input wire number;
• means responsive to reading of said input wire number instruction for retrieving the status of said input wire number from said wire number memory and, if in "on" state, setting a first one of said storage devices under said clock control;
• means responsive to reading of said special code for setting a second one of said storage devices under said clock control indicative of an output action;
• and means for providing an output signal under said clock control provided said first and second storage devices are set.

In a programmable controller:

• main memory means for storing sets of instructions defining the configuration of a ladder diagram, at least one of said sets of instructions including the input wire number to an output device, a special code indicative of an output action, and the output device number;
• means for performing an AND-logic function and storing the result comprising:
• means for reading said instructions of said sets from said main memory in sequence;
• a plurality of signal storage devices;
• a control clock;
• an addressable wire number memory for storing the status of said input wire number;
• an addressable control coil memory for storing the status of control coils;
• means responsive to reading of said input wire number instruction for retrieving the status of said input wire number from said wire number memory and, if in "on" state, setting a first one of said storage devices under said clock control;
• means responsive to reading of said special code for setting a second one of said storage devices under said clock control indicative of an output action;
• means for providing an output signal under said clock control provided said first and second storage devices are set;
• and means responsive to said reading of said output device number instruction and responsive to said output device number being a control coil number and to said output signal for writing the "on" state of said control coil number in said control coil memory.

In a programmable controller, means for performing an AND/OR-logic function and storing the result comprising:

• a plurality of flip-flops;
• a control clock;
• means for processing a first series circuit to provide an AND-logic function of state signals comprising:
• means responsive to a first state signal for setting or resetting the first flip-flop under said clock control according to whether said first state signal is "1" or "0";
• means responsive to a second state signal representing a serial circuit relationship with said first state signal for setting or resetting the second flip-flop under said clock control according to whether said second state signal is "1" or "0" as well as whether said first flip-flop is set or reset;
• means for directly setting or not setting the third flip-flop under said clock control according to whether said second flip-flop is set or reset;
• means for normally storing the state of said third flip-flop and then resetting the same under said clock control when an OR-logic function is not involved;
• means responsive to an OR-logic function signal for deferring the storing of the state of said third flip-flop and for inhibiting the resetting of the latter;
• means for processing a second series circuit whose output is connected to the output of said first series circuit to provide an OR-logic function comprising:
• means responsive to a first state signal of said second series circuit for setting or resetting said first flip-flop under said clock control according to whether this signal is "1" or "0";
• means responsive to a second state signal of said second series circuit representing a serial circuit relationship with the last mentioned signal for setting or resetting said second flip-flop according to whether this second state signal is "1" or "0" as well as whether said first flip-flop is set or reset;
• means for directly setting said third flip-flop if it is in reset state or leaving it in set state if it is in set state, or not setting in according to whether said second flip-flop is set or reset;
• and means for storing the state of said third flip-flop and then resetting the same under said clock control.

In a programmable controller:

• a main memory with a ladder-diagram-defining program stored therein, said program defining said ladder diagram with sets of three, unidirectional-logic instructions such that each ladder daigram control contact and input device of a plurality thereof is defined in terms of the input wire number thereto, the control contact or input device number, and the output wire number therefrom, and each ladder diagram output element, including each control coil, of a plurality thereof is defined in terms of the input wire number to such element, a special non-addressing code indicative of an output action, and the control coil or other output element number, and said control coils being identified by numbers falling in a different range from the number range identifying input devices and other output elements;
• addressable input circuits including said input devices and output circuits including said output elements having addresses corresponding to said input device numbers and said output elements numbers;
• and central processing means comprising:
• a control clock;
• auxiliary memory means comprising an addressable wire number memory having addresses corresponding to said input wire numbers and said output wire numbers for receiving, storing and making available the on-off status of said input and output wire numbers;
• an address generator operated by said clock for addressing said main memory to read said instructions therefrom in sequence;
• means for applying said main memory instructions to address said auxiliary memory means including said addressable wire number memory and said addressable input and output circuits;
• and logic circuit means including said auxiliary memory means comprising means controlled by said clock upon reading of said instructions of each said set in sequence for providing status signals for said input wire number and control contact or input device, means AND'ing said status signals to provide the output wire number status, means for storing said output wire number status in said wire number memory, means for retrieving the latter when the next set of instructions is read as indicative of the on-off status of the input wire number of the next series-connected control contact or input device, and means for providing an output signal to said output circuit when the last instruction set of a series circuit is read which is an output device instruction set.