US 4,227,045 A · Data processing protocol system

Abstract

A transceiver circuit for connecting a data processing unit to a communication bus, wherein said data processing unit is capable of transmitting, receiving and processing non-return to zero (NRZ) signals having a normally high level and assuming a low level to indicate a data bit and said communication bus is capable of transmitting a pulse-no pulse signal to indicate data bits, is disclosed having an input connected to the data processing unit for receiving the non-return to zero signals, a triggering circuit which is responsive to a leading edge of a non-return to zero signal to supply triggering pulses having a predetermined frequency, a gating circuit for passing through the triggering pulses as long as the non-return to zero signal is at a predetermined level, and a pulse-no pulse circuit responsive to the triggering pulses for supplying the pulse-no pulse signals to the communication bus. In addition, the receive portion of the transceiver circuit is responsive to the pulse-no pulse signals to convert them into non-return to zero signals.

Claims24

Dependent claims

A transceiver circuit for connecting a data processing unit to a communication bus, said data processing unit capable of transmitting, receiving and processing non-return to zero signals having a normal first level and assuming a second level to indicate a data bit and said communication bus capable of transmitting pulses to communicate a data bit, said transceiver circuit comprising:

an input connected to said data processing unit for receiving non-return to zero signals to be transmitted;
triggering means connected to said input and responsive to an edge of a non-return to zero signal to be transmitted to begin supplying triggering pulses having a predetermined frequency;
gate means connected to both said triggering means and said input for passing said triggering pulses through as long as said non-return to zero signals to be transmitted are at their second level;
pulse-no pulse means connected to said gate means and responsive to said triggering pulses for supplying said pulses to said communication bus;
receive means connected to said communication bus for receiving pulses from said communication bus and converting them to non-return to zero signals to be processed;
and,
means connected to said receive means and to said data processing unit for transmitting said non-return to zero signals to be processed to said data processing means.

4 more elements

A transceiver circuit for connecting a data processing unit to a communication bus, said data processing unit capable of transmitting, receiving and processing non-return to zero signals having a normal first level and assuming a second level to indicate a data bit and said communication bus capable of transmitting pulses to indicate a data bit, said transceiver circuit comprising:

transmit means connected to said data processing unit for receiving non-return to zero signals to be transmitted and converting them to pulses to be transmitted;
means connecting said transmit means to said communication bus;
input means connected to said communication bus for receiving pulses to be processed;
connecting means for connecting said pulses to be processed from said input means to an output;
first switching means having a normal first level output connected to said output of said connecting means and responsive to said pulses to be processed to switch said first level output to a second level output;
and,
means for connecting said output of said switching means to said data processing unit.

4 more elements

Dependencies are inferred from the claim text.

Data processing protocol system

Life of this patent

Data processing protocol system

Life of this patent

Abstract

Claims24