Method of reducing emitter dip in transistors utilizing specifically paired dopants

A method of manufacturing a semiconductor device which comprises the steps of:

• providing an N type collector layer in an N type silicon semiconductor wafer having a substantially flat surface;
• coating said N type collector layer with a first oxide film layer;
• forming a first opening in said first oxide film layer such that a portion of the surface of said N type collector layer is exposed;
• depositing a layer doped with an N type impurity having a high energy of combination with vacancies on said N type collector layer exposed by said first opening;
• diffusing said N type impurity from said N type impurity doped layer into said N type collector layer;
• removing said N type impurity doped layer from said N type collector layer;
• depositing a boron doped layer on said N type collector layer exposed by said first opening;
• diffusing boron from said boron doped layer into said N type collector layer such that a P type base layer in contact with said N type collector layer having a PN junction extending to said surface is formed;
• removing said boron doped layer from said N type collector;
• covering said N type collector layer and said P type base layer with a second oxide film layer;
• forming a second opening in said second oxide film layer, said second opening being smaller than said first opening in said first oxide film layer;
• and
• diffusing phosphorus and arsenic which are N type impurities through said second opening in said second oxide layer into said P type base layer such that an N type emitter layer is formed which is in contact with said P type base layer having a PN junction extending to said surface and which constitutes a transistor together with said N type collector layer and said P type base layer.